Optimal infinite scheduling for multi-priced timed automata

This paper is concerned with the derivation of infinite schedules for timed automata that are in some sense optimal. To cover a wide class of optimality criteria we start out by introducing an extension of the (priced) timed automata model that includes both costs and rewards as separate modelling features. A precise definition is then given of what constitutes optimal infinite behaviours for this class of models. We subsequently show that the derivation of optimal non-terminating schedules for such double-priced timed automata is computable. This is done by a reduction of the problem to the determination of optimal mean-cycles in finite graphs with weighted edges. This reduction is obtained by introducing the so-called corner-point abstraction, a powerful abstraction technique of which we show that it preserves optimal schedules. This work has been mostly done while visiting CISS at Aalborg University in Denmark and has been supported by CISS and by ACI Cortos, a program of the French Ministry of Research.     

新闻动态Q＆A Linn Olofsdotter

这是一位四海为家的瑞典籍天才运动图形插画家,她将会为你展示自己对肌理的热衷以及为什么你无需害怕黑暗的一面……     

Information Seeking Can Be Social

For reasons ranging from obligation to curiosity, users have a strong inclination to seek information from others during the search process. Search systems using statistical analytics over traces left behind by others can help support the search experience.     

Deposition thickness based high-throughput nano-imprint template

International Technology Roadmap for Semiconductors 2003 projected nano-imprint lithography has the potential of high throughput, sub-20 nm resolution, and low cost [S.Y. Chou, P.R. Krauss, P.J. Renstrom, Appl. Phys. Lett. 67 (1995) 3144; Science 272 (1996) 85, J.A. Rogers, C. Mirkin, Mater. Res. Bull. 26 (2001)]. For nano-imprint lithography, a template with 1X resolution is required. The existing industrial infrastructure for supporting deep ultra violet 4X photo masks by e-beam and/or a laser beam scanning writer does not offer pitch (center-to-center distance of an array of patterned lines) less than ∼60 nm [<http://public.itrs.net/2003ITRS>]. For nano-imprint lithography to be accepted across the industry, a reproducible simple fabrication process to make a high resolution, single emboss template is essential [L. Jay Guo, J. Phys. D: Appl. Phys. 37 (2004) R123-R141]. Here we show, a general fabrication method and fabricated nano-imprint templates with sub-15 nm template line width and 10 nm pitch length through out the entire 200 mm wafer, varying the deposition thickness of multiple alternate films, using atomic layer deposition. Although multilayer nano-imprint templates and their exciting use have been demonstrated, [W.J. Dauksher et al., J. Vac. Sci. Technol. B 22 (2004) 3306, B. Heidari, et al., The 49th international conference on electron, ion and photon beam technology and nanofabrication, Orlando, Florida, 2005, William M. Tong, et al., Proc. SPIE 5751 (2005) 46-55, N.A. Melosh, A. Boukai, F. Diana, B. Gerardot, A. Badolato, P.M. Petroff, J.R. Heath, Science 300 (2003) 112] such a small pitch was not shown and either complex lattice mismatch-based epitaxially grown films or unconventional etch chemistry was used. The bare necessity was a simple and economical fabrication process for a high throughput nano-imprint template. In that context, we have developed a template fabrication process using classical micro-fabrication techniques. Successful use of these techniques made the template fabrication process simple, economical, and expedient. Also a novel technique to provide flexible and accurate alignment for nanowire patterning has been described. In this technique, nanowire patterning is accomplished on the entire wafer with a single impression. Industry level batch-fabrication of our scheme illustrates its reproducibility and manufacturability. We anticipate, this simple, economical and time saving technique will help researchers and developers to perform their experiment on nano-scale feature patterned substrates easily and conveniently.     

光定时系统设计

2003.3/下半月 www.eepw.com.cn电子产品世界本文给出一个简单、完整的传感器基测量系统设计，该系统是用测量两个光束隔断的时间来测量运动物体的速度。此设计包括显示和状态指示器、时间保持和控制功能所需的所有数字逻辑以及连接提供光感测功能的IR(红外)LED和光二极管所必须的模拟信号处理。系统测量经过时间范围是毫秒~分钟量级。本系统有4个主要的子系统(见图1)：用户接口，传感器接口/接收器，计数器/显示逻辑和主机控制逻辑。用户接口由7位LED数字显示(显示经过时间)、几个状态LED和两个按钮开关(RESE…     

Three-Stage Thin-Film Superlattice Thermoelectric Multistage Microcoolers with a Δ<Emphasis Type="Italic">T</Emphasis><Subscript>max</Subscript> of 102 K

Thin-film Bi₂Te₃- and Sb₂Te₃-based superlattice (SL) thermoelectric (TE) devices are an enabling technology for high-power and low-temperature applications, which include low-noise amplifier cooling, electronics hot-spot cooling, radio frequency (RF) amplifier thermal management, and direct sensor cooling. Bulk TE devices, which can pump heat loads on the order of 10 W/cm², are not suitable in these applications due to their large size and low heat pumping capacity. Recently, we have demonstrated an external maximum temperature difference, ΔT _max, as high as 58 K in an SL thin-film p–n couple. This state-of-the-art couple exhibited a cold-side minimum temperature, T _cmin, of −30.9°C. We regularly attain ΔT _max values in excess of 53 K, in spite of the many significant electrical and thermal parasitics that are unique to thin-film devices. These measurements do not use any complex thermal management at the heat sink to remove the heat flux from the TE device’s hot side. We describe here multistage SL cooling technologies currently being developed at RTI that can provide useful microcooling cold-side temperatures of 200 K. This effort includes a three-stage module employing independently powered stages which produced a ΔT _max of 101.6 K with a T _cmin of −75°C, as well as a novel two-wire three-stage SL cascade which demonstrated a T _cmin of −46°C and a ΔT _max of nearly 74 K. These RTI modules are only 2.5 mm thick, significantly thinner than a similar commercial three-stage module (5.3 mm thick) that produces a ΔT _max of 96 K. In addition, TE coolers fabricated from these thin-film SL materials perform significantly better than the extrapolated performance of similar thickness bulk alloy materials.     

A fully pipelined RLS-based array for channel equalization

It is shown that several recursive least squares (RLS) type equalization algorithms such as, e.g., decisiondirected schemes and orthogonalized constant modulus algorithms, possess a common algorithmic structure and are therefore rather straightforwardly implemented on an triangular array (filter structure) for RLS estimation with inverse updating. While the computational complexity for such algorithms isO(N ²), whereN is the problem size, the throughput rate for the array implementation isO(1), i.e., independent of the problem size. Such a throughput rate cannot be achieved with standard (Gentleman-Kung-type) RLS/QR-updating arrays because of feedback loops in the computational schemes.     

部署40G技术正当时

当今业内普遍达成的一个共识是运营商不应单纯为追求高速度的虚名而采用40G技术，应该等待40G技术具备与现有技术相当的性价比，也就是说，当40G技术的成本降至10G技术的四倍以下时才予以采用。然而，对于何时能够降至四倍以下，则众说纷纭。例如，有人指出当前40G技术的成本是10G技术的十倍。在本文中，我们将分析40G传输技术应用障碍如何被夸大或误解，同时指出目前已投入商用的40G产品的成本已不足10G技术的四倍。从理论上讲，40G线路信号所要求的光信噪比（OSNR）高出10G信号6分贝，这意味着10G信号可以不经再生传输更远的距离。…     

A Methodology for Architecture Exploration of Heterogeneous Signal Processing Systems

We present a methodology for the exploration of signal processing architectures at the system level. The methodology, named SPADE, provides a means to quickly build models of architectures at an abstract level, to easily map applications, modeled as Kahn Process Networks, onto these architecture models, and to analyze the performance of the resulting system by simulation. The methodology distinguishes between applications and architectures, and uses a trace-driven simulation technique for co-simulation of application models and architecture models. As a consequence, architecture models need not be functionally complete to be used for performance analysis while data dependent behavior is still handled correctly. We have used the methodology for the exploration of architectures and mappings of an MPEG-2 video decoder application.