Exposed Die-Top Encapsulation Molding for an Improved High- Performance Flip Chip BGA Package

The recent advancement in high- performance semiconductor packages has been driven by the need for higher pin count and superior heat dissipation. A one-piece cavity lid flip chip ball grid array (BGA) package with high pin count and targeted reliability has emerged as a popular choice. The flip chip technology can accommodate an I/O count of more than five hundreds500, and the die junction temperature can be reduced to a minimum level by a metal heat spreader attachment. None the less, greater expectations on these high-performance packages arose such as better substrate real estate utilization for multiple chips, ease in handling for thinner core substrates, and improved board- level solder joint reliability. A new design of the flip chip BGA package has been looked into for meeting such requirements. By encapsulating the flip chip with molding compound leaving the die top exposed, a planar top surface can be formed. A, and a flat lid can then be mounted on the planar mold/die top surface. In this manner the direct interaction of the metal lid with the substrate can be removed. The new package is thus less rigid under thermal loading and solder joint reliability enhancement is expected. This paper discusses the process development of the new package and its advantages for improved solder joint fatigue life, and being a multichip package and thin core substrate options. Finite-element simulations have been employed for the study of its structural integrity, thermal, and electrical performances. Detailed package and board-level reliability test results will also be reported     

Intelligent process analytics for CRM

Many organisations use decision models in their processes such as tables or trees to provide decision support to their operational divisions. For example, in fault management, customer contact centre operators usually use a decision model in the form of prescribed interviews. Based on the answers given by customers, the operator navigates through the decision model to reach an assessment of the problem. In order to achieve customer satisfaction and operational excellence, it is very important to constantly monitor the performance of a decision model not only on an overall level, but also on the level of individual decisions. In this paper we present a configurable business process analytics tool, known as the intelligent Universal Service Management System, that constantly monitors decision data and is capable of optimising the decisions based on high-level business objectives. We explain the various features of the software and show how it can be used to optimise decision processes. We also show how we can easily provide a customised version to monitor the performance of provision processes.     

High-performance MIM capacitor using ALD high-k HfO/sub 2/-Al/sub 2/O/sub 3/ laminate dielectrics

For the first time, we successfully fabricated and demonstrated high performance metal-insulator-metal (MIM) capacitors with HfO/sub 2/-Al/sub 2/O/sub 3/ laminate dielectric using atomic layer deposition (ALD) technique. Our data indicates that the laminate MIM capacitor can provide high capacitance density of 12.8 fF//spl mu/m/sup 2/ from 10 kHz up to 20 GHz, very low leakage current of 3.2 /spl times/ 10/sup -8/ A/cm/sup 2/ at 3.3 V, small linear voltage coefficient of capacitance of 240 ppm/V together with quadratic one of 1830 ppm/V/sup 2/, temperature coefficient of capacitance of 182 ppm//spl deg/C, and high breakdown field of /spl sim/6 MV/cm as well as promising reliability. As a result, the HfO/sub 2/-Al/sub 2/O/sub 3/ laminate is a very promising candidate for next generation MIM capacitor for radio frequency and mixed signal integrated circuit applications.     

A 1-V 10.7-MHz switched-opamp bandpass /spl Sigma//spl Delta/ modulator using double-sampling finite-gain-compensation technique

A 1 V switched-capacitor (SC) bandpass sigma-delta (/spl Sigma//spl Delta/) modulator is realized using a high-speed switched-opamp (SO) technique with a sampling frequency of up to 50 MHz, which is improved ten times more than prior 1 V SO designs and comparable to the performance of the state-of-the-art SC circuits that operate at much higher supply voltages. On the system level, a fast-settling double-sampling SC biquadratic filter architecture is proposed to achieve high-speed operation. A low-voltage double-sampling finite-gain-compensation technique is employed to realize a high-resolution /spl Sigma//spl Delta/ modulator using only low-DC-gain opamps to maximize the speed and to reduce power dissipation. On the circuit level, a fast-switching methodology is proposed for the design of the switchable opamps to achieve a switching frequency up to 50 MHz. Implemented in a 0.35-/spl mu/m CMOS process (V/sub TP/=0.82 V and V/sub TN/=0.65 V) and at 1 V supply, the modulator achieves a measured peak signal-to-noise-and-distortion ratio (SNDR) of 42.3 dB at 10.7 MHz with a signal bandwidth of 200 kHz, while dissipating 12 mW and occupying a chip area of 1.3 mm/sup 2/.     

Position-sensitive superheated-liquid-droplet neutron dosimeter

The one-dimensional (1D) position-sensitive superheated-liquid-droplet dosimeter (SLDD) has been fabricated and tested in the laboratory. The 1D SLDD is fabricated from a 9.525-mm OD, 6.35-mm ID, 20-cm long, Plexiglas-walled tube filled with a mixture of superheated-liquid Freon droplets and host medium glycerol. Washer-shaped piezoelectric acoustic transducers are positioned at both ends of the tube; they determine the number and positions of the acoustic events when the superheated-liquid droplets evaporate upon neutron irradiation. The SLDD is irradiated with the ¹³⁷Cs and ⁶⁰Co γ-sources, as well as ²⁵²Cf neutron source to test for its radiation response and spatial resolution. The SLDD based on the Freon-134a superheated-liquid droplets operating at 20°C and 1 atm is found to be ideal for measuring absorbed neutron dose. This study also proves that the positions of the radiation-induced nucleation acoustic events can be linearly determined from the differences in the transmission times received by the acoustic transducers on the 1D SLDD. The spatial resolution of the neutron depth-dose is 1 mm due the finite response time (1 μs) of the piezoelectric acoustic transducers.     

C-t analysis of MOS capacitors under constant current stress

The effect of high oxide field stress is studied using capacitance-time (C-t) measurements of MOS capacitors. The stress results in parallel shifts of the C-t curve along the time axis. The flatband voltage shift ΔV_FB obtained from the initial deep depletion capacitance C(t=0⁺) follows the same trend as that from the high-frequency C-V characteristics. However, the discrepancy between the two flatband voltages becomes larger as the stress increases due to the effect of interface charges on C-t characteristics. The flatband voltage difference is converted to interface trap density, showing a steady increase of interface trap density with stress, similar to that from low-frequency C-V measurements     

Recording of volume hologram using a beam pattern from taperedoptical fiber

A photorefractive volume hologram was recorded and probed using light diffracted from a tapered optical fiber as a reference beam. A single-mode fiber (SMF) was chemically etched and tapered to give a complicated beam pattern, and it is shown that the tapered optical fiber can be utilized to increase the storage density of the volume hologram. Spatial selectivity of the volume hologram with this method was increased by two times compared to the normal SMF referencing, which is due to the fact that the complicated beam pattern has little correlation with its shifted version     

Modeling of laser keyhole welding: Part I. mathematical modeling,numerical methodology,role of recoil pressure,multiple reflections,and free surface evolution

A three-dimensional laser-keyhole welding model is developed, featuring the self-consistent evolution of the liquid/vapor (L/V) interface together with full simulation of fluid flow and heat transfer. Important interfacial phenomena, such as free surface evolution, evaporation, kinetic Knudsen layer, homogeneous boiling, and multiple reflections, are considered and applied to the model. The level set approach is adopted to incorporate the L/V interface boundary conditions in the Navier-Stokes equation and energy equation. Both thermocapillary force and recoil pressure, which are the major driving forces for the melt flow, are incorporated in the formulation. For melting and solidification processes at the solid/liquid (S/L) interface, the mixture continuum model has been employed. The article consists of two parts. This article (Part I) presents the model formulation and discusses the effects of evaporation, free surface evolution, and multiple reflections on a steady molten pool to demonstrate the relevance of these interfacial phenomena. The results of the full keyhole simulation and the experimental verification will be provided in the companion article (Part II).     

Holographic polymer‐dispersed liquid crystal fabrication under electric field

The transmission mode of holographic polymer‐dispersed liquid crystals (HPDLCs) was developed an under electric field. It is reported that orientation of LC molecules under an electric field induces orientation of oligomer molecules giving rise to low off‐state diffraction and small grating shrinkage. Copyright © 2005 Society of Chemical Industry     

A single-chip storage LSI for home networks

Network direct attached storage (NDAS) is a network storage architecture that allows direct attachment of existing ATA/ATAPI devices to Ethernet without a separate server. Unlike other architectures such as NAS, SAN, and USB mass storage, no server computer intervenes between the storage and the client hosts. We describe an NDAS disk controller (NDC) amenable to low-cost single-chip implementation that processes a simplified L3/L4 protocol and converts commands between ATA/ATAPI and Ethernet, while the remaining complex tasks are performed by remote hosts. Unlike NAS architectures that use TCP/IP, NDAS uses a TCP-like lean protocol that lends itself well to high-performance hardware realization. Thanks to the simple NDAS architecture and protocol, an NDC implemented on a single 4 mm /spl times/ 4 mm chip in 0.18 /spl mu/m CMOS technology achieves a maximum throughput of 55 Mbytes/s on gigabit Ethernet, which is comparable to that of a high-performance disk locally attached to a host computer.