Robust Estimation of Rotation Angles from Image Sequences Using the Annealing M-Estimator

A robust method is presented for computing rotation angles of image sequences from a set of corresponding points containing outliers. Assuming known rotation axis, a least-squares (LS) solution are derived to compute the rotation angle from a clean data set of point correspondences. Since clean data is not guaranteed, we introduce a robust solution, based on the M-estimator, to deal with outliers. Then we present an enhanced robust algorithm, called the annealing M-estimator (AM-estimator), for reliable robust estimation. The AM-estimator has several attractive advantages over the traditional M-estimator: By definition, the AM-estimator involves neither scale estimator nor free parameters and hence avoids instabilities therein. Algorithmically, it uses a deterministic annealing technique to approximate the global solution regardless of the initialization. Experimental results are presented to compare the performance of the LS, M- and AM-estimators for the angle estimation. Experiments show that in the presence of outliers, the M-estimator outperforms the LS estimator and the AM-estimator outperforms the M-estimator.     

微单来袭：索尼全新EVIL机型NEX-5C发布

随着可换镜头类单反相机在市场上风生水起,影像业界的知名大厂商索尼（SONY）也耐不住寂寞了。2010年6月9日,索尼在北京发布了基于全新E-mount卡口的新品NEX-5C,被誉为微单相机的它采用了与可换镜头类单反相机一样的光学结构,还配有APS-C画幅的传感器。     

高标清混合格式的广播世界

本将针对电视台从标清格式向标清与高清格式混合播出进行改造所需要考虑到的问题进行讨论。要想做到这一点就要找到满带宽基带运行模式与信号压缩模式的平衡点。     

5-GHz 32-bit integer execution core in 130-nm dual-V/sub T/ CMOS

A 32-bit integer execution core containing a Han-Carlson arithmetic-logic unit (ALU), an 8-entry /spl times/ 2 ALU instruction scheduler loop and a 32-entry /spl times/ 32-bit register file is described. In a 130 nm six-metal, dual-V/sub T/ CMOS technology, the 2.3 mm/sup 2/ prototype contains 160 K transistors. Measurements demonstrate capability for 5-GHz single-cycle integer execution at 25/spl deg/C. The single-ended, leakage-tolerant dynamic scheme used in the ALU and scheduler enables up to 9-wide ORs with 23% critical path speed improvement and 40% active leakage power reduction when compared to a conventional Kogge-Stone implementation. On-chip body-bias circuits provide additional performance improvement or leakage tolerance. Stack node preconditioning improves ALU performance by 10%. At 5 GHz, ALU power is 95 mW at 0.95 V and the register file consumes 172 mW at 1.37 V. The ALU performance is scalable to 6.5 GHz at 1.1 V and to 10 GHz at 1.7 V, 25/spl deg/C.     

Glycopeptide obtained from k-casein and its effect on protein assimilation

The products of restricted proteolysis of kappa-casein were separated by gel filtration. Intravenous injection of high- and low-molecular fractions substantially reduced the pentagastrin-stimulated acid secretion in the anesthetized rat stomach. Intermediate fractions had lesser physiological activity. One of the active fractions administered intraintestinally inhibited acid secretion and reduced the pentagastrin-stimulated secretion in rat weanling isolated stomach. All the active fractions inhibited the stimulated secretion in rats with a ligated vagus. It is concluded that the nervous system does not play a crucial role in the mechanism by which gastric acid secretion is inhibited by the products of restricted proteolysis of kappa-casein. Decreasing acid secretion in the stomach, glycopeptide provides for the conditions favouring the efficacy of protein utilization at an early age. It is suggested that the effect of glycopeptide obtained from kappa-casein on the process of assimilation is mediated via peptide hormones.     

Analysis of dual-VT SRAM cells with full-swingsingle-ended bit line sensing for on-chip cache

This paper compares different high-V_T and dual-V_T design choices for a large on-chip cache with single-ended sensing in a 0.13 μm technology generation. The analysis shows that the best design is the one using a dual-V_T cell, with minimum channel length pass transistors, and low-V_T peripheral circuits. This dual-V_T circuit provides 20% performance gain with only 1.3× larger active leakage power, and 2.4% larger cell area compared to the best design using high-V_T cells with nonminimum channel length pass transistors     

Life prediction of LED-based recess downlight cooled by synthetic jet

This paper details the adaptation and implementation of a proposed hierarchical model to the reliability assessment of LED-based luminaires. An Edison base ? 6 in., compatible can, downlight ? LED replacement bulb, cooled by active synthetic jets, is used as the test vehicle. Based on the identified degradation mechanisms and the experimentally obtained degradation rate of the cooling device, the reduction in the heat sink enhancement factor, and thus the increase in the LED junction temperature, is determined as a function of time. The degradation mechanisms of the dual-function power electronics – providing constant power to the LEDs and to the drivers of a series of synthetic jets – are also analyzed and serve as the basis for a hybrid model which combines these two effects on the luminaire lifetime. The lifetime of a prototypical luminaire is predicted from LED lifetime data using the degradation analyses of the synthetic jet and power electronics.     

HotSpot: a compact thermal modeling methodology for early-stage VLSI design

This paper presents HotSpot-a modeling methodology for developing compact thermal models based on the popular stacked-layer packaging scheme in modern very large-scale integration systems. In addition to modeling silicon and packaging layers, HotSpot includes a high-level on-chip interconnect self-heating power and thermal model such that the thermal impacts on interconnects can also be considered during early design stages. The HotSpot compact thermal modeling approach is especially well suited for preregister transfer level (RTL) and presynthesis thermal analysis and is able to provide detailed static and transient temperature information across the die and the package, as it is also computationally efficient.     

Conformational Molecular Switches for Post-CMOS Nanoelectronics

Theoretical treatments forecast that bistable CMOS devices using electronic charge as a state variable will operate at their maximum thermal dissipation limit possibly as early as 2012. The problem is further compounded by increasing manufacturing challenges associated with the ever decreasing logic switch dimensions. These challenges require the development of new fabrication strategies that replace or complement current top-down lithography with bottom-up protocols using controlled self-assembly of nanomaterial building blocks. To answer some of these issues, this paper focuses on a new device paradigm consisting of an arene-metal-arene conformational switch, addressable through capacitive, inductive, or resonant-tunneling field coupling. The operating principle is based on voltage-tunable modulation in quantum electron transmission. The switch is open (off) when the metal ion is displaced to a position at a C-H bond on the arene ring due to an externally applied bias. Conversely, when the external bias is removed, the metal ion moves to an axis- symmetric position on the arene ring, and the switch is closed (on). The paper presents a summary of the architecture, operating principle, and advantages of the conformational switch, along with associated findings from proof-of-concept theoretical and experimental studies of its target specifications and performance. The paper also discusses opportunities and challenges related to the integration of conformational switches into hybrid CMOS-molecular and monolithic (all molecular) circuits.