Setting the trap for hot carriers [MOS VLSI]

The device degradation under ac and dc stress have been discussed and a relationship between the two has been established,. We have shown that the commonly used lifetime criteria of 10% linear current degradation for 10 years for a transistor under dc stress is overly conservative for representing the circuit operating lifetime. Using experimental and simulated data for inverter chains, we proposed that a meaningful equivalent lifetime based on 10% I_dl degradation under dc stress is 1 year lifetime (for a 10 year circuit lifetime based on 54b degradation in ring oscillator frequency). We also compared this criteria to actual circuit degradation for microprocessors and a DRAM. For DSP microprocessors with 0.8 μm LDD transistors, the projected lifetime was more than 200 years at 5.5 V, with a corresponding 10% I _dr lifetime of 20 years. For 1 Mb DRAMs with 1 pm LDD transistors, the 5% speed degradation lifetime at 5.5 V was more than 100 years, whereas the individual transistors had 10% I_dl lifetime of 4 years. These circuit results support the 10% I_dl transistor lifetime. We believe these criterion should be very safe and reasonable for digital IC chips currently in the field, as well as those in future design and development     

Analysis of gate-bias-induced heating effects in deep-submicron ESD protection designs

This paper presents a detailed investigation of the degradation of electrostatic discharge (ESD) strength with high gate bias for deep-submicron salicided ESD protection nMOS transistors, which has significant implications for protection designs where high gate coupling occurs under ESD stress. It has been shown that gate-bias-induced heating is the primary cause of early ESD failure and that this impact of gate bias depends on the finger width of the protection devices. In addition, it has been established that substrate biasing can effectively alleviate the adverse impact of the gate bias and can improve ESD strength despite the gate-coupling level. Improved understanding of ESD behavior for advanced devices under high gate-coupling conditions can extend design capabilities of protection structures.     

Internal chip ESD phenomena beyond the protection circuit

Input/output electrostatic discharge (ESD) circuit requirements call for good protection of the pin with respect to both the ground and the power bus pins. Although effective protection can be designed at the pin many cases of damage phenomena are known to occur internal to the chip beyond the protection circuit. Here, the issues of protection between V_DD and V_SS are discussed first. This is followed by examples of how protection circuit performance can be sensitive to internal chip layout, independent of its effective design. Several illustrative actual case studies are reported to emphasize the internal chip ESD phenomena and their adverse effects     

Leakage current degradation in n-MOSFETs due to hot-electron stress

The field-induced drain-leakage current can become significant in NMOS devices with thin gate oxides. This leakage current component is found to be more prominent in devices with gate-drain overlap and can increase considerably with hot-electron stress. A method which shows how measuring the gate voltage needed to obtain a constant leakage value of 0.1 nA can yield useful information on the interface charge trap density is discussed     

ESD: a pervasive reliability concern for IC technologies

Several aspects of ESD are described from the point of view of the test, design, product, and reliability engineering. A review of the ESD phenomena along with the test methods, the appropriate on-chip protection techniques, and the impact of process technology advances from CMOS to BiCMOS on the ESD sensitivity of IC protection circuits are presented. The status of understanding in the field of ESD failure physics and the current approaches for modeling are discussed     

Development of substrate-pumped nMOS protection for a 0.13 μm technology

A methodology is presented for improved process and circuit development of substrate-pumped nMOS protection. ESD process development is accelerated by applying factor analysis to completed non-ESD experiments. Factor analysis is complemented by a straightforward diagnosis of nMOS snapback. This approach enabled verification of two process solutions, including a novel method, in one fab cycle-time. HBM data that shows the substrate-pumped nMOS can provide dramatically higher protection than estimated from conventional I_t2 measurements. This motivates improved ESD circuit development. The nMOS clamp transistor is characterized as an actively biased LNPN, which is how it is used in a substrate-pumped protection circuit. A systematic approach to circuit development is described that is based upon empirical characterization of well-defined circuit components under conditions approximating ESD.     

Analysis of nonuniform ESD current distribution in deep submicron NMOS transistors

This paper presents a detailed study of the nonuniform bipolar conduction phenomenon under electrostatic discharge (ESD) events in single-finger NMOS transistors and analyzes its implications for the design of ESD protection for deep-submicron CMOS technologies. It is shown that the uniformity of the bipolar current distribution under ESD conditions is severely degraded depending on device finger width (W) and significantly influenced by the substrate and gate-bias conditions as well. This nonuniform current distribution is identified as a root cause of the severe reduction in ESD failure threshold current for the devices with advanced silicided processes. Additionally, the concept of an intrinsic second breakdown triggering current (I/sub t2i/) is introduced, which is substrate-bias independent and represents the maximum achievable ESD failure strength for a given technology. With this improved understanding of ESD behavior involved in advanced devices, an efficient design window can be constructed for robust deep submicron ESD protection.     

Electrical overstress and electrostatic discharge

Semiconductor devices have a limited ability to sustain electrical overstress (EOS). The device susceptibility to EOS increases as the device is scaled down to submicron feature size. At present, EOS is a major cause for IC failures. Published reports indicate that nearly 40% of IC failures can be attributed to EOS events. Hence, EOS threats must be considered early in the design process. For semiconductor devices, EOS embodies a broad range of electrical threats due to electromagnetic pulses, electrostatic discharge (ESD), system transients, and lightning. EOS-related failures in semiconductor devices can be classified according to their primary failure mechanisms into: thermally-induced failures, electromigration, electric-field-related failures. In general, thermally-induced failures are related to the doping level, junction depth, and device characteristic-dimensions whereas electric-field induced failures are primarily related to the breakdown of thin oxides in MOS devices