A 100-V lateral DMOS transistor with a 0.3-micrometer channel in a1-micrometer silicon-film-on-insulator-on-silicon

A novel LDMOS transistor structure with breakdown voltages above 100 V has been fabricated in silicon-on-insulator-on-silicon (SOIS). This structure has been fabrication by silicon direct bonding (SDB) and etch-back to a typical film thickness of 1 μm. The silicon carrier layer (handle) serves as a back-gate electrode, which, under proper bias, improves the transistor characteristics significantly. The effective channel length or basewidth is 0.3 μm. Under these conditions, the drift region becomes the current-limiting element. The physics in the drift region in thin silicon films (⩽1 μm) in the transistor on-state is dominated by the injected electrons from the channel. The limitation of the maximum drain current is given by the quasi-saturation effect. Criteria for the further optimization of SOIS LDMOS transistors are presented     

A 150-V multiple up-drain VDMOS, CMOS, and bipolar process in`direct-bonded' silicon on insulator on silicon

Silicon on insulator on silicon (SOIS) has been produced with silicon direct bonding (SDB). Within a silicon film of 15-μm thickness, islands with ubiquitous oxide isolation have been formed for the simultaneous integration of 150-V power VDMOS transistors, CMOS circuits in a channelless sea-of-gates array with 2-μm gates, and bipolar transistors. The up-drain VDMOS transistors with 2-Ω-mm ² specific on-resistance allow multiple isolated outputs, so high-voltage push-pull drivers can be fabricated in a single chip. The bipolar transistors are comparable to those of a 60-V standard process with vertical n-p-n and lateral p-n-p current gains of 80