A new and accurate fault location algorithm for combined transmission lines using Adaptive Network-Based Fuzzy Inference System

This paper presents a new and accurate algorithm for locating faults in a combined overhead transmission line with underground power cable using Adaptive Network-Based Fuzzy Inference System (ANFIS). The proposed method uses 10 ANFIS networks and consists of 3 stages, including fault type classification, faulty section detection and exact fault location. In the first part, an ANFIS is used to determine the fault type, applying four inputs, i.e., fundamental component of three phase currents and zero sequence current. Another ANFIS network is used to detect the faulty section, whether the fault is on the overhead line or on the underground cable. Other eight ANFIS networks are utilized to pinpoint the faults (two for each fault type). Four inputs, i.e., the dc component of the current, fundamental frequency of the voltage and current and the angle between them, are used to train the neuro-fuzzy inference systems in order to accurately locate the faults on each part of the combined line. The proposed method is evaluated under different fault conditions such as different fault locations, different fault inception angles and different fault resistances. Simulation results confirm that the proposed method can be used as an efficient means for accurate fault location on the combined transmission lines.     

A novel low voltage very low power CMOS class AB current output stage with ultra high output current drive capability

In this paper a novel low voltage (LV) very low power (VLP) class AB current output stage (COS) with extremely high linearity and high output impedance is presented. A novel current splitting method is used to minimize the transistors gate–source voltages providing LV operation and ultra high current drive capability. High linearity and very high output impedance are achieved employing a novel resistor based current mirror avoiding conventional cascode structures to be used. The operation of the proposed COS has been verified through HSPICE simulations based on TSMC 0.18 μm CMOS technology parameters. Under supply voltage of ±0.7 V and bias current of 5 μA, it can deliver output currents as high as 14 mA with THD better than ?53 dB and extremely high output impedance of 320 MΩ while consuming only 29 μW. This makes the proposed COS to have ultra large current drive ratio (I_outmax/I_bias or the ratio of peak output current to the bias current of output branch transistors) of 2800. By increasing supply voltage to ±0.9 V, it can deliver extremely large output current of ±24 mA corresponding to 3200 current drive ratio while consuming only 42.9 μW and exhibiting high output impedance of 350 MΩ. Interestingly, the proposed COS is the first yet reported one with such extremely high output current and a THD even less than ?45 dB. Such ultra high current drive capability, high linearity and high output impedance make the proposed COS an outstanding choice for LV, VLP and high drive current mode circuits. The superiority of the proposed COS gets more significance by showing in this work that conventional COS can deliver only ±3.29 mA in equal condition. The proposed COS also exhibits high positive and negative power supply rejection ratio (PSRR+/PSRR?) of 125 dB and 130 dB, respectively. That makes it very suitable for LV, VLP mixed mode applications. The Monte Carlo simulation results are provided, which prove the outstanding robust performance of the proposed block versus process tolerances. Favorably the proposed COS resolves the major limitation of current output stages that so far has prevented designing high drive current mode circuits under low supply voltages. In brief, the deliberate combination of so many effective novel methods presents a wonderful phenomenal COS block to the world of science and engineering.     

High Gain Modified Dual-Band and Dual-Circularly Polarized Array Antenna

Wireless Personal Communications - A novel design of double-layer dual-band circularly polarized array antennas (DDCPAAs) is presented in this paper. First, a DDCP single antenna is introduced as...     

The S-transform using a new window to improve frequency and time resolutions

The S-transform presents arbitrary time series as localized invertible time–frequency spectra. This transformation improves the short-time Fourier transform and the wavelet transform by merging the multiresolution and frequency-dependent analysis properties of wavelet transform with the absolute phase retaining of Fourier transform. The generalized S-transform utilizes a combination of a Fourier transform kernel and a scalable-sliding window. The common S-transform applies a Gaussian window to provide appropriate time and frequency resolution and minimizes the product of these resolutions. However, the Gaussian S-transform is unable to obtain uniform time and frequency resolution for all frequency components. In this paper, a novel window based on the $t$ student distribution is proposed for the S-transform to achieve a more uniform resolution. Simulation results show that the S-transform with the proposed window provides in comparison with the Gaussian window a more uniform resolution for the entire time and frequency range. The result is suitable for applications such as spectrum sensing.     

Generalized carrier to interference ratio analysis for shotgun cellular systems in multiple dimensions over composite Rayleigh–Lognormal (Suzuki) fading

Telecommunication Systems - This paper analyzes the carrier-to-interference ratio (CIR) of the so-called shotgun cellular systems (SCSs) in $$\tau $$ dimensions ( $$\tau =1, 2,$$ and 3). SCSs are...     

Wideband Frequency-Reconfigurable Antenna for Airborne Applications

Wireless Personal Communications - One of the important objectives of underwater acoustic sensor network is to extend the lifespan of a network which depends on the topology control mechanisms....     

All two-input logic gates by a single-stage single electron box

In this paper, the design of all two-input logic gates is presented by only a single-stage single electron box (SEB) for the first time. All gates are constructed based on a same circuit. We have used unique periodic characteristics of SEB to design these gates and present all two-input logic gates (monotonic/non-monotonic, symmetric/non-symmetric) by a single-stage design. In conventional monotonic devices, such as MOSFETs, implementing non-monotonic logic gates such as XOR and XNOR is impossible by only a single-stage design, and a multistage design is required which leads to more complexity, higher power consumption and less speed of the gates. We present qualitative design at first and then detailed designs are investigated and optimised by using our previous works. All designs are verified by a single electron simulator which shows correct operation of the gates.     

Energy efficiency optimization of one-way and two-way DF relaying considering circuit power

In this paper, the energy efficiency (EE) of a decode and forward (DF) relay system is studied, where two sources communicate through a half-duplex relay node in one-way and two-way relaying strategies. Both the circuitry power and the transmission power of all nodes are taken into consideration. In addition, three different coding schemes for two-way DF relaying strategy with two phases and two-way DF relaying with three phases are considered. The aim is to maximize the EE of the system for a constant spectral efficiency (SE). For this purpose, the transmission time and the transmission power of each node are optimized. Simulations are used to compare the EE–SE curve of different DF strategies with one-way and two-way amplify and forward (AF) strategies and direct transmission (DT), to find the best energy efficient strategy in different SE conditions. Analytical and simulation results demonstrate that in low SE conditions, DF relaying strategies are more energy efficient compared to that of AF strategies and DT. However, in high SE conditions, the EE of two-way AF relaying and DT strategy outperform some of the DF relaying strategies. In simulations, the impact of different circuitry power and different channel conditions on the EE–SE curves are also investigated.