Algorithm for Increasing the Speed of Evolutionary Optimization and its Accuracy in Multi-objective Problems

Optimization algorithms are important tools for the solution of combinatorial management problems. Nowadays, many of those problems are addressed by using evolutionary algorithms (EAs) that move toward a near-optimal solution by repetitive simulations. Sometimes, such extensive simulations are not possible or are costly and time-consuming. Thus, in this study a method based on artificial neural networks (ANN) is proposed to reduce the number of simulations required in EAs. Specifically, an ANN simulator is used to reduce the number of simulations by the main simulator. The ANN is trained and updated only for required areas in the decision space. Performance of the proposed method is examined by integrating it with the non-dominated sorting genetic algorithm (NSGAII) in multi-objective problems. In terms of density and optimality of the Pareto front, the hybrid NSGAII-ANN is able to extract the Pareto front with much less simulation time compared to the sole use of the NSGAII algorithm. The proposed NSGAII-ANN methodology was examined using three standard test problems (FON, KUR, and ZDT1) and one real-world problem. The latter addresses the operation of a reservoir with two objectives (meeting demand and flood control). Thus, based on this study, use of the NSGAII-ANN integrative algorithm in problems with time-consuming simulators reduces the required time for optimization up to 50 times. Results of the real-world problem, despite lower computational-time requirements, show a performance similar to that achieved in the aforementioned test problems.     

A SAR-based ΣΔ modulator using shared DAC

In this paper a new successive approximation (SA) quantizer based on the elimination of the digital to analog converter (DAC) from the quantizer structure is presented. Instead; the feedback DAC block of the ΣΔ modulator is shared by SA quantizer. Using an efficient decoding algorithm in the proposed structure in conjunction with the above SA quantizer DAC elimination method, results in a reduction of the level number of the feedback DAC, and hence, a significant drop in power and area consumption is achieved. In order to study the performance of the proposed structure, a third order discrete-time ΣΔ modulator is designed and simulated in 0.18 μm CMOS technology with the following performance characteristics; a signal to noise ratio of 79.2 dB, dynamic range of 84.8 dB, power consumption of 3.75 mW and a figure of merit of 0.66 pJ/conv from a 1.8 V supply with an input signal of 200 kHz bandwidth.     

Differential current conveyor based current comparator

A New differential current conveyor based current comparator is presented in this paper. Differential current conveyor II (DCCII) is designed, modified, and exploited as a comparator with reduced propagation delay and power consumption. New DCCII decreases propagation delay and increases comparator accuracy considerably. Simulation results using Hspice and 0.18 μm CMOS technology with 1.8V supply voltage confirms a less than 0.63 ns propagation delay at ±1 μA input current. Average power dissipation in ±1 μA input current has a value of 300 μW.     

Fuzzy-based multiscale edge detection

A new fuzzy-based multiscale edge detection technique is presented. The proposed approach achieves optimal edge detection using the wavelet decomposition of the original signal followed by a novel fuzzy-based decision technique that is applied across the scales. Results indicate a significant improvement in locating edges compared to other multiscale approaches.     

An Anti-Gray Hole Attack Scheme in Mobile Ad Hoc Network

International Journal of Wireless Information Networks - Dynamic variation of network topology in mobile ad hoc networks (MANET) forces network nodes to work together and rely on each other for...     

Differential Cascode Voltage Switch (DCVS) Strategies by CNTFET Technology for Standard Ternary Logic

Differential Cascode Voltage Switch (DCVS) is a well-known logic style, which constructs robust and reliable circuits. Two main strategies are studied in this paper to form static DCVS-based standard ternary fundamental logic components in digital electronics. While one of the strategies leads to fewer transistors, the other one has higher noise margin. New designs are simulated with HSPICE and 32 nm CNTFET technology at various realistic conditions such as different power supplies, load capacitors, frequencies, and temperatures. Simulations results demonstrate their robustness and efficiency even in the presence of PVT variations. In addition, new noise injection circuits for ternary logic are also presented to perform noise immunity analysis.     

High-Performance Mixed-Mode Universal Min-Max Circuits for Nanotechnology

In this paper a low-power, high-speed and high-resolution voltage-mode Min-Max circuit, as well as a new efficient universal structure for determining the minimum and maximum values of the input digital signals, is proposed for nanotechnology. In addition, the proposed designs provide rail-to-rail input and output signals which enhance the performance and the robustness of the circuits. The advantage of the proposed Min-Max circuit is that it is extendable for any arbitrary n-digit and radix-r input numbers. Comprehensive simulation results at CMOS and CNFET technologies demonstrate the low-power and high-performance operation as well as insusceptibility to PVT variations of the proposed structure.     

Two new low-power Full Adders based on majority-not gates

Two novel low-power 1-bit Full Adder cells are proposed in this paper. Both of them are based on majority-not gates, which are designed with new methods in each cell. The first cell is only composed of input capacitors and CMOS inverters, and the second one also takes advantage of a high-performance CMOS bridge circuit. These kinds of designs enjoy low power consumption, a high degree of regularity, and simplicity. Low power consumption is targeted in implementation of our designs. Eight state-of-the-art 1-bit Full Adders and two proposed Full Adders are simulated using 0.18 μm CMOS technology at many supply voltages. Simulation results demonstrate improvement in terms of power consumption and power-delay product (PDP).