High-temperature electrical characteristics of GaAs MESFETs(25-400°C)

The effects of elevated ambient and substrate temperatures (25°C up to 400°C) on the electrical characteristics of integrated GaAs MESFETs in a state-of-the-art commercial technology are reported. The focus is on the large- and small-signal parameters of the transistors. The existence of zero-temperature-coefficient drain currents is demonstrated analytically and experimentally for enhancement- and for depletion-mode GaAs MESFETs. The data show that, while GaAs MESFETs generally display degradation mechanisms similar to those of silicon MOSFETs with increasing temperature, they incur several additional effects, prominent among which are increased gate leakage currents, lowered Schottky-barrier height, decreased large- and small-signal (gate) input resistances, decreased sensitivity to sidegating and backgating up to approximately 200°C, and increased small-signal drain resistance     

Low programming voltage floating gate analogue memory cells in standard VLSI CMOS technology

Floating gate MOSFET structures were fabricated in a standard 2 mu m double-polysilicon CMOS process which requires programming voltages of only 6.5-9 V. This considerable reduction in programming voltage is achieved by simultaneously exploiting tunnelling through the interpolysilicon oxide and capacitive geometries whose top poly-layers overlap the edges of the lower poly-layers.<>     

Electrical characteristics of large scale integration (LSI) MOSFETs at very high temperatures part II: Experiment

An experimental investigation of the effects of high temperature (25°C to 300°C) on N and P channel MOS transistors is reported. At the device level, the temperature dependences of the electrical parameters are characterized individually; they include the threshold voltage, the channel mobility, and junction leakage currents. Drain current I–V characteristics are obtained for each of the subthreshold, nonsaturation, and saturation regions of operation, with temperature as a parameter. Zero-Temperature-Coefficient (ZTC) points' properties are found to be in good agreement with the theory.     

CMOS logic cell switching speed thermal characterisation

A study of the switching speed performance of basic CMOS logic cells in the (junction) temperature range 25?250°C is reported. Experimental measurements for capacitively loaded inverters and NAND gates of two standard 4 ?m CMOS processes are compared to theory and to SPICE2G. 6 simulations. It is found that, to a good approximation, a simple delineation factor (lying between 0.004 and 0.006/deg C in this study), applied to the average gate delay at a given temperature, correctly predicts this parameter. Logic cells are thereby typically found to be up to 65% slower at 250°C than they are at room temperature.     

Comparison of floating gate neural network memory cells in standardVLSI CMOS technology

Several floating gate MOSFET structures, for potential use as analog memory elements in neural networks, have been fabricated in a standard 2 mum double-polysilicon CMOS process. Their physical and programming characteristics are compared with each other and with similar structures reported in the literature. None of the circuits under consideration require special fabrication techniques. The criteria used to determine the structure most suitable for neural network memory applications include the symmetry of charging and discharging characteristics, programming voltage magnitudes, the area required, and the effectiveness of geometric field enhancement techniques. This work provides a layout for an analog neural network memory based on previously unexplored criteria and results. The authors have found that the best designs (a) use the poly1 to poly2 oxide for injection; (b) need not utilize ;field enhancement' techniques; (c) use poly1 to diffusion oxide for a coupling capacitor; and (d) size capacitor ratios to provide a wide range of possible programming voltages.     

Analysis and modeling of nonlinearities in VLSI MOSFETs includingsubstrate effects

Presents a detailed analysis of the distortion components of the drain current of integrated MOS transistors operated in nonsaturation, in which signals are simultaneously applied to the drain, gate, and substrate terminals. In contrast with previous analyses which have accounted for the modulation of the inversion layer channel mobility by both transverse and longitudinal fields (short channel devices), the model yields highly accurate analytical expressions in closed form (down to at least 80 dB below fundamental), and hence easily lends itself to 'hand' analysis. Moreover, the model predicts that individual odd or even distortion components can be suppressed (nulled) by a range of combinations of substrate bias and signal amplitudes. Alternatively, odd distortion components can be nulled by suitable substrate drive while even distortion components can be nulled by properly driving the gate terminals of the MOSFETs. Experimental data which validate the model are presented, and the effectiveness of harmonic suppression in a standard, tunable, MOSFET-C integrator is demonstrated     

Small-signal drain conductance of MOSFET in saturation region?a simple model

A simple expression is developed which determines an upper bound on the incremental drain conductance of the long-channel MOSFET in saturation. This expression may be used to estimate efficiently lower gain bounds of MOS gain stages at the hand analysis phase of analogue circuit designs. The accuracy achieved is comparable to that of currently used commercial simulators and to the data spread observed in current MOS processes. A criterion for `long?-channel behaviour in saturation is proposed.     

Electrical characteristics of large scale integration (LSI) MOSFETs at very high temperatures part I: Theory

A systematic investigation of the effects of high temperature (27° C to 300° C) on long N and P channel MOS transistors suitable for Large Scale Integration (LSI) is presented. The theory of the MOSFET is used to study the temperature behavior of the device's electrical parameters. The main temperature dependent parameters are the threshold voltage, the channel mobility, and the junction leakage currents. Zero-Temperature-Coefficient (ZTC) gate bias voltages are predicted, in the nonsaturation (linear) region, and in the saturation region of operation, for a given device. Criteria for the existence of such bias points are developed, and nonidealities of these points discussed. The large and small signal parameters of the MOSFET biased at its ZTC points are obtained. Detailed comparisons with experimental results will be reported in an accompanying paper [1].