排序方式: 共有33条查询结果,搜索用时 0 毫秒
1.
为适应拔尖创新人才培养的需要,提高工程图学教学效果,本文提出了工程图学课程的改革方案,进行了实践研究。采用中英双语教学模式,开展基于构型创新设计的工程图学实验课与自主型交互式机械设计制图实验课。培养了学生的创新思维与工程意识,锻炼了其动手实践能力,提高了学生团队合作素质,为专业知识的学习打好基础,取得了理想的教学效果。 相似文献
2.
3.
实施双语教学是“2+2”中外联合培养模式的要求,在这些学生中开展双语教学是必需的.该文就工程图学课程的特点,分析了双语教学的基本现状、教学目标和教学难点等问题.力求通过对课程在结构设置上进行调整与改革,达到联合培养模式的要求. 相似文献
4.
考虑到温度和工艺参数浮动的影响,对休眠双阈值footed多米诺电路的漏电流特性进行了系统的量化研究和比较,得到了不同温度下的最佳休眠状态.基于65和45nm BSIM4模型的HSPICE仿真表明:与业已提出的CHIL(时钟为高,输入均为低电平)状态和CHIH(时钟和输入均为高电平)状态相比,本文提出的CLIL(时钟和输入均为低电平)状态更有利于减小低温下电路的漏电流和高温下的多扇人电路的漏电流.而且,分析了工艺参数的浮动对双阈值footed多米诺电路的漏电流特性的影响,并给出了温度和工艺参数浮动下,双阈值footed多米诺电路漏电流最小的休眠状态. 相似文献
5.
Using the multiple-parameter Monte Carlo method, the effectiveness of the dual threshold voltage technique (DTV) in low power domino logic design is analyzed. Simulation results indicate that under significant temperature and process fluctuations, DTV is still highly effective in reducing the total leakage and active power consumption for domino gates with speed loss. Also, regarding power and delay characteristics, different structure domino gates with DTV have different robustness against temperature and process fluctuation. 相似文献
6.
A novel technique using a keeper with a simultaneous low supply voltage and low body voltage is proposed to improve the overall performance of high fan-in OR gates without modifying the physical dimensions of the keeper.Simulation results of a 16-input domino OR gate using 45 nm CMOS technology show that the proposed technique could trade off between a high power/speed efficient operation and the robustness to noise effectively.Also,a Monte Carlo analysis indicates that the proposed domino OR gate is more robust to parameter variation compared to a conventional domino OR gate. 相似文献
7.
低功耗、高性能多米诺电路电荷自补偿技术 总被引:1,自引:0,他引:1
提出了一种电荷自补偿技术来降低多米诺电路的功耗,并提高了电路的性能.采用电荷自补偿技术设计了具有不同下拉网络(PDN)和上拉网络(PUN)的多米诺电路,并分别基于65,45和32nm BSIM4 SPICE模型进行了HSPICE仿真.仿真结果表明,电荷自补偿技术在降低电路功耗的同时,提高了电路的性能.与常规多米诺电路技术相比,采用电路自补偿技术的电路的功耗延迟积(PDP)的改进率可达42.37%.此外,以45nm Zipper CMOS全加器为例重点介绍了功耗分布法,从而优化了自补偿路径,达到了功耗最小化的目的.最后,系统分析了补偿通路中晶体管宽长比,电路输入矢量等多方面因素对补偿通路的影响. 相似文献
8.
考虑到温度和工艺参数浮动的影响,对休眠双阈值footed多米诺电路的漏电流特性进行了系统的量化研究和比较,得到了不同温度下的最佳休眠状态.基于65和45nm BSIM4模型的HSPICE仿真表明:与业已提出的CHIL(时钟为高,输入均为低电平)状态和CHIH(时钟和输入均为高电平)状态相比,本文提出的CLIL(时钟和输入均为低电平)状态更有利于减小低温下电路的漏电流和高温下的多扇入电路的漏电流.而且,分析了工艺参数的浮动对双阈值footed多米诺电路的漏电流特性的影响,并给出了温度和工艺参数浮动下,双阈值footed多米诺电路漏电流最小的休眠状态. 相似文献
9.
Non-contact atomic force microscopy(nc-AFM) atomic-scale imaging process of monocrystalline silicon surface using capped single-wall carbon nanotube tip is simulated by molecular dynamic method. The simulation results show that the nc-AFM imaging force mainly comes from the C-Si and C-C chemical covalent bonding forces, especially the former, the nonbonding Van der Waals force change is small during the range of stable imaging height. When the tip-surface distance is smaller than the stable imaging height, several neighboring carbon atoms at the tip apex are attracted, and some of them jump onto the sample surface. Finally the tip apex configuration is destroyed with the tip indenting further. 相似文献
10.
利用休眠晶体管、多阈值和SEFG技术(源跟随求值门技术),设计了一种新型的p结构多米诺与门.HSPICE仿真结果表明,在相同的时间延迟下,与标准双阈值多米诺与门、标准低阈值多米诺与门和SEFG结构相比,提出的新型多米诺与门的漏电流分别减小了43%,62%和67%,噪声容限分别增大了3.4%,23.6%和13.7%.从而有效地解决了亚65nm工艺下多米诺与门存在的漏电流过大,易受干扰的问题.分析并得到了不同结构的休眠多米诺与门的漏电流最低的输入矢量和时钟状态. 相似文献