Erosion-corrosion behavior of SiC particle-reinforced Al-Si alloy in NaOH slurry

The erosion-corrsosion behavior of SiC particle-reinforced Al-Si alloy has been studied in NaOH slurry simulating the mining atmosphere. The study was performed at two different sand concentrations, namely, 20 and 30 wt pct, and at a speed of 900 rpm. It is depicted that the wear rates decreased with increasing sand content, indicating that corrosion is the dominating mode of material removal. Further composite exhibited lower wear resistance than the laloys irrespective of the sand concentration. Scanning electron microscope (SEM) observations indicated the dissolution of dendrites of Al due to severe corrosion, leaving behind the network of Si. This ultimately results in the falling of Si particles from the matrix, leaving behind voids. This also results in the formation of voids around the SiC particles and leads to pullout of SiC particles from the matrix during the wear process.     

Plasmon‐Induced Hot Carrier Separation across Dual Interface in Gold–Nickel Phosphide Heterojunction for Photocatalytic Water Splitting

Precise control of the topology of metal nanocrystals and appropriate modulation of the metal–semiconductor heterostructure is an important way to understand the relationship between structure and material properties for plasmon‐induced solar‐to‐chemical energy conversion. Here, a bottom‐up wet chemical approach to synthesize Au/Ni₂P heterostructures via Pt‐catalyzed quasi‐epitaxial overgrowth of Ni on Au nanorods (NR) is presented. The structural motif of the Ni₂P is controlled using the aspect ratio of the Au NR and the effective micelle concentration of the C₁₆TAB capping agent. Highly ordered Au/Pt/Ni₂P nanostructures are employed as the photoelectrocatalytic anode system for water splitting. Electrochemical and ultrafast absorption spectroscopy characterization indicates that the structural motif of the Ni₂P (controlled by the outer‐shell deposition of Ni) helps to manipulate hot electron transfer during surface plasmon decay. With optimized Ni₂P thickness, Pt‐tipped Au NR with an aspect ratio of 5.2 exhibits a geometric current density of 10 mA cm^?2 with an overpotential of 140 mV. The photoanode displays unprecedented long‐term stability with continuous chronoamperometric performance of 50 h at an input potential of 1.5 V with over 30 days. This work provides definitive guidance for designing plasmonic–catalytic nanomaterials for enhanced solar‐to‐chemical energy conversion.     

Transition‐Metal Dichalcogenide NiTe2: An Ambient‐Stable Material for Catalysis and Nanoelectronics

By means of theory and experiments, the application capability of nickel ditelluride (NiTe₂) transition‐metal dichalcogenide in catalysis and nanoelectronics is assessed. The Te surface termination forms a TeO₂ skin in an oxygen environment. In ambient atmosphere, passivation is achieved in less than 30 min with the TeO₂ skin having a thickness of about 7 Å. NiTe₂ shows outstanding tolerance to CO exposure and stability in water environment, with subsequent good performance in both hydrogen and oxygen evolution reactions. NiTe₂‐based devices consistently demonstrate superb ambient stability over a timescale as long as one month. Specifically, NiTe₂ has been implemented in a device that exhibits both superior performance and environmental stability at frequencies above 40 GHz, with possible applications as a receiver beyond the cutoff frequency of a nanotransistor.     

Composition,structure and electrical properties of DC reactive magnetron sputtered Al2O3 thin films

Thin films of alumina (Al₂O₃) were deposited over Si 〈1 0 0〉 substrates at room temperature at an oxygen gas pressure of 0.03 Pa and sputtering power of 60 W using DC reactive magnetron sputtering. The composition of the as-deposited film was analyzed by X-ray photoelectron spectroscopy and the O/Al atomic ratio was found to be 1.72. The films were then annealed in vacuum to 350, 550 and 750 °C and X-ray diffraction results revealed that both as-deposited and post deposition annealed films were amorphous. The surface morphology and topography of the films was studied using scanning electron microscopy and atomic force microscopy, respectively. A progressive decrease in the root mean square (RMS) roughness of the films from 1.53 nm to 0.7 nm was observed with increase in the annealing temperature. Al–Al₂O₃–Al thin film capacitors were then fabricated on p-type Si 〈1 0 0〉 substrate to study the effect of temperature and frequency on the dielectric property of the films and the results are discussed.     

Analysis of Test Application Time for Test Data Compression Methods Based on Compression Codes

We present an analysis of test application time for test data compression techniques that are used for reducing test data volume and testing time in system-on-a-chip (SOC) designs. These techniques are based on data compression codes and on-chip decompression. The compression/decompression scheme decreases test data volume and the amount of data that has to be transported from the tester to the SOC. We show via analysis as well as through experiments that the proposed scheme reduces testing time and allows the use of a slower tester. Results on test application time for the ISCAS'89 circuits are obtained using an ATE testbench developed in VHDL to emulate ATE functionality.     

Balance testing and balance-testable design of logic circuits

We propose a low-cost method for testing logic circuits, termed balance testing, which is particularly suited to built-in self testing. Conceptually related to ones counting and syndrome testing, it detects faults by checking the difference between the number of ones and the number of zeros in the test response sequence. A key advantage of balance testing is that the testability of various fault types can be easily analyzed. We present a novel analysis technique which leads to necessary and sufficient conditions for the balance testability of the standard single stuck-line (SSL) faults. This analysis can be easily extended to multiple stuck-line and bridging faults. Balance testing also forms the basis for design for balance testability (DFBT), a systematic DFT technique that achieves full coverage of SSL faults. It places the unit under test in a low-cost framework circuit that guarantees complete balance testability. Unlike most existing DFT techniques, DFBT requires only one additional control input and no redesign of the underlying circuit is necessary. We present experimental results on applying balance testing to the ISCAS 85 benchmark circuits, which show that very high fault coverage is obtained for large circuits even with reduced deterministic test sets. This coverage can always be made 100% either by adding tests or applying DFBT.This research was supported by the National Science Foundation under Grant No. MIP-9200526. Parts of this paper were published in preliminary form in Proc. 23rd Symp. Fault-Tolerant Computing, Toulouse, June 1993, and in Proc. 31st Design Automation Conf, San Diego, June 1994.     

Comparative Study on the Properties of Galvanically Deposited Nano- and Microcrystalline Thin Films of PbSe

Thin films of PbSe having both nano- and microstructures have been deposited on transparent conducting oxide (TCO)-coated glass substrates electrochemically, from an aqueous solution of Pb(OAc)₂, ethylenediamine tetraacetic acid (EDTA), and SeO₂. A Pb strip acted as the sacrificial anode, while the TCO glass was the cathode. No external bias was applied. The formation of PbSe was pH sensitive, and pH ~3 was found to be optimum for film deposition. Films grown at room temperature (25°C) were nanocrystalline (~25 nm), while those deposited at 80°C were microcrystalline (~150 nm). Films were characterized by x-ray diffraction studies, field-emission scanning electron microscope image analysis, infrared spectral analysis, and by both alternating-current (a.c.) and direct-current (d.c.) electrical measurements. A blue-shift was observed for the nanocrystalline films. Film resistivity and junction properties were obtained from electrical measurements.     

Channel Adaptive Quantization for Limited Feedback MIMO Beamforming Systems

Multiple-input multiple-output (MIMO) wireless systems can achieve significant diversity and array gain by using transmit beamforming and receive combining techniques. In the absence of full channel knowledge at the transmitter, the transmit beamforming vector can be quantized at the receiver and sent to the transmitter using a low-rate feedback channel. In the literature, quantization algorithms for the beamforming vector are designed and optimized for a particular channel distribution, commonly the uncorrelated Rayleigh distribution. When the channel is not uncorrelated Rayleigh, however, these quantization strategies result in a degradation of the receive signal-to-noise ratio (SNR). In this paper, switched codebook quantization is proposed where the codebook is dynamically chosen based on the channel distribution. The codebook adaptation enables the quantization to exploit the spatial and temporal correlation inherent in the channel. The convergence properties of the codebook selection algorithm are studied assuming a block-stationary model for the channel. In the case of a nonstationary channel, it is shown using simulations that the selected codebook tracks the distribution of the channel resulting in improvements in SNR. Simulation results show that in the case of correlated channels, the SNR performance of the link can be significantly improved by adaptation, compared with nonadaptive quantization strategies designed for uncorrelated Rayleigh-fading channels     

MESFET MMIC Ka-band transmitter performance forhigh-volume system applications

An MMIC transmitter for high-volume smart munition applications in Ka band is developed using 0.25 μm MESFET technology. The transmitter, consisting of a voltage-controlled oscillator (VCO) and power amplifier (PA), delivers more than 100 mW of power with an overall efficiency of 10% and a linear tuning range of more than 700 MHz around 35 GHz     

Optimization Methods for Post-Bond Testing of 3D Stacked ICs

Testing of three-dimensional (3D) stacked ICs (SICs) is starting to receive considerable attention in the semiconductor industry. Since the die-stacking steps of thinning, alignment, and bonding can introduce defects, there may be a need to test multiple subsequent partial stacks during 3D assembly. We address the problem of test-architecture optimization for 3D stacked ICs to minimize overall test time when either the complete stack only, or the complete stack and multiple partial stacks, need to be tested. A general solution to this problem provides several options for 3D stack testing in a unified framework. We show that optimal test-architecture solutions and test schedules for multiple test insertions are different from their counterparts for a single final stack test. In addition, we present optimization techniques for the testing of TSVs and die-external logic in combination with the dies in the stack.