A power-driven multiplication instruction-set design method for ASIPs

This paper presents a novel power-driven multiplication instruction-set design method for application-specific instruction-set processors (ASIPs). Based on a dual-and-configurable-multiplier structure, our proposed method devises a multiplication instruction set for low-power ASIPs. Our method exploits the execution sequences of multiplication instructions and effective bit widths of variables to reduce power consumed by redundant multiplication bits while minimizing the multiplication execution time. Experimental results on a set of DSP programs demonstrate that our proposed method achieves significant power reduction (up to 18.53%) and execution time improvement (up to 10.43%) with 18% area overhead.     

Microstrip stepped impedance resonator bandpass filter with an extended optimal rejection bandwidth

Bandpass filters with an optimal rejection bandwidth are designed using parallel-coupled stepped impedance resonators (SIRs). The fundamental (f/sub o/) and higher order resonant harmonics of an SIR are analyzed against the length ratio of the high-Z and low-Z segments. It is found that an optimal length ratio can be obtained for each high-Z to low-Z impedance ratio to maximize the upper rejection bandwidth. A tapped-line input/output structure is exploited to create two extra transmission zeros in the stopband. The singly loaded Q(Q/sub si/) of a tapped SIR is derived. With the aid of Q/sub si/, the two zeros can be independently tuned over a wide frequency range. When the positions of the two zeros are purposely located at the two leading higher order harmonics, the upper rejection band can be greatly extended. Chebyshev bandpass filters with spurious resonances up to 4.4f/sub o/, 6.5f/sub o/, and 8.2f/sub o/ are fabricated and measured to demonstrate the idea.     

A robust classification procedure based on mixture classifiers and nonparametric weighted feature extraction

There are many factors to consider in carrying out a hyperspectral data classification. Perhaps chief among them are class training sample size, dimensionality, and distribution separability. The intent of this study is to design a classification procedure that is robust and maximally effective, but which provides the analyst with significant assists, thus simplifying the analyst's task. The result is a quadratic mixture classifier based on Mixed-LOOC2 regularized discriminant analysis and nonparametric weighted feature extraction. This procedure has the advantage of providing improved classification accuracy compared to typical previous methods but requires minimal need to consider the factors mentioned above. Experimental results demonstrating these properties are presented.     

一种用于SOC设计中的智能I/O处理器的实现

文章介绍了SOC设计流程，智能I／O处理器组成，在开发该处理器对VHDL源代码的优化问题。     

关于化粪池几个问题的探讨

探讨化粪池在设计布置及使用管理中应注意的几个问题，以充分发挥化粪池在保护环境，减轻污染方面的作用。     

High-resolution electron microscopy of the twinning and intergrowth in Ca4Al6SO16 and Ca3SrAl6SO16

The microstructures of unhydrated calcium aluminosulphate Ca₄Al₆SO₁₆ and Ca₃SrAl₆SO₁₆ have been studied by high-resolution electron microscopy (HREM). The results showed that twinning and twinned slabs could be introduced taking the [1 1 2] direction as the twin axis so that it seems to be coincident with the law of twinning formed in body-centred cubic structures. A previously reported superlattice with a repeat period twice that of the fundamental structure along the 〈1 1 0〉 direction has also been found in both matrix and twin variants. The close intergrowth of Ca₃SrAl₆SO₁₆ and another phase, possibly Sr₃Al₂O₆ existing as an inclusion between these two twin variants, was determined and clearly revealed by electron diffraction and HREM images. The coherent interphase boundaries and orientation relationship between them can also be deduced.     

A BiCMOS dynamic carry lookahead adder circuit for VLSIimplementation of high-speed arithmetic unit

A BiCMOS dynamic carry lookahead circuit that is free from race problems is presented. A 16 b full-adder test circuit, which has been designed based on a 2 μm BiCMOS technology, shows a more than five times improvement in speed as compared to the CMOS Manchester carry lookahead (MCLA) circuit. The speed advantage of the BiCMOS dynamic carry lookahead circuit is even greater in a 32- or 64-b adder     

Cluster analysis in industrial market segmentation through artificial neural network

Market segmentation has commonly applied cluster analysis. This study intends to make the comparison of conventional two-stage method with proposed two-stage method through the simulated data. The proposed two-stage method is the combination of self-organizing feature maps and K-means method. The simulation results show that the proposed scheme is better than the conventional two-stage method based on the rate of misclassification.