High-performance MIM capacitor using ALD high-k HfO/sub 2/-Al/sub 2/O/sub 3/ laminate dielectrics

For the first time, we successfully fabricated and demonstrated high performance metal-insulator-metal (MIM) capacitors with HfO/sub 2/-Al/sub 2/O/sub 3/ laminate dielectric using atomic layer deposition (ALD) technique. Our data indicates that the laminate MIM capacitor can provide high capacitance density of 12.8 fF//spl mu/m/sup 2/ from 10 kHz up to 20 GHz, very low leakage current of 3.2 /spl times/ 10/sup -8/ A/cm/sup 2/ at 3.3 V, small linear voltage coefficient of capacitance of 240 ppm/V together with quadratic one of 1830 ppm/V/sup 2/, temperature coefficient of capacitance of 182 ppm//spl deg/C, and high breakdown field of /spl sim/6 MV/cm as well as promising reliability. As a result, the HfO/sub 2/-Al/sub 2/O/sub 3/ laminate is a very promising candidate for next generation MIM capacitor for radio frequency and mixed signal integrated circuit applications.     

Reliability investigation of 0.07-/spl mu/m InGaAs-InAlAs-InP HEMT MMICs with pseudomorphic In/sub 0.75/Ga/sub 0.25/As channel

The authors have investigated the reliability performance of G-band (183 GHz) monolithic microwave integrated circuit (MMIC) amplifiers fabricated using 0.07-/spl mu/m T-gate InGaAs-InAlAs-InP HEMTs with pseudomorphic In/sub 0.75/Ga/sub 0.25/As channel on 3-in wafers. Life test was performed at two temperatures (T/sub 1/ = 200 /spl deg/C and T/sub 2/ = 215 /spl deg/C), and the amplifiers were stressed at V/sub ds/ of 1 V and I/sub ds/ of 250 mA/mm in a N/sub 2/ ambient. The activation energy is as high as 1.7 eV, achieving a projected median-time-to-failure (MTTF) /spl ap/ 2 /spl times/ 10/sup 6/ h at a junction temperature of 125 /spl deg/C. MTTF was determined by 2-temperature constant current stress using /spl Delta/G/sub mp/ = -20% as the failure criteria. The difference of reliability performance between 0.07-/spl mu/m InGaAs-InAlAs-InP HEMT MMICs with pseudomorphic In/sub 0.75/Ga/sub 0.25/As channel and 0.1-/spl mu/m InGaAs-InAlAs-InP HEMT MMICs with In/sub 0.6/Ga/sub 0.4/As channel is also discussed. The achieved high-reliability result demonstrates a robust 0.07-/spl mu/m pseudomorphic InGaAs-InAlAs-InP HEMT MMICs production technology for G-band applications.     

Dynamic programming implementation on array processor architectures

Dynamic Programming (DP) applies to many signal and image processing applications including boundary following, the Viterbi algorithm, dynamic time warping, etc. This paper presents an array processor implementation of generic dynamic programming. Our architecture is a SIMD array attached to a host computer. The processing element of the architecture is based on an ASIC design opting for maximum speed-up. By adopting a torus interconnection network, a dual buffer structure, and a multilevel pipeline, the performance of the DP chip is expected to reach the order of several GOPS. The paper discusses both the dedicated hardware design and the data flow control of the DP chip and the total array.This work was supported in part by the NATO, Scientific and Environmental Affairs Division, Collaborative Research Grant SA.5-2-05(CRG.960201)424/96/JARC-501.     

89-GHz fT room-temperature silicon MOSFETs

The authors report the implementation of deep-submicrometer Si MOSFETs that at room temperature have a unity-current-gain cutoff frequency (f_T) of 89 GHz, for a drain-to-source bias of 1.5 V, a gate-to-source bias of 1 V, a gate oxide thickness of 40 Å, and a channel length of 0.15 μm. The fabrication procedure is mostly conventional, except for the e-beam defined gates. The speed performance is achieved through an intrinsic transit time of only 1.8 ps across the active device region     

Differences in risk factors for being either a hepatitis B carrier or anti-hepatitis C+ in a hepatoma-hyperendemic area in rural Taiwan

This is a study of the differences in the risk factors for being either hepatitis B surface antigen positive [HBsAg(+)] or antibody to hepatitis C virus positive [Anti-HCV(+)] in A-Lein, a rural area in southern Taiwan, an area which also has a high hepatoma mortality rate. Three hundred eighty-five patients age > or =40 years participated in hepatoma screening at the A-Lein Community Health Center during 1995. Those who were HBsAg(-) and anti-HCV(-) or had coinfection of HBsAg(+) and anti-HCV(+) were excluded, leaving 293 patients: 109 HBsAg(+) and 184 anti-HCV(+). The anti-HCV(+) patients had a lower socioeconomic status (as defined by level of education and type of occupation) and were older than HBsAg(+) patients (P < 0.05). Those with higher alanine aminotransferase levels (ALT) also had a higher anti-HCV(+) to HBsAg(+) odds ratio (OR), and a dose response relationship was found, P < 0.0001. Anti-HCV(+) patients were more likely than HBsAg(+) patients to have a spouse who shared the infection, OR = 5.11; 95% CI, 2.30-11.28. Anti-HCV(+) patients were more likely than HBsAg(+) patients to have had blood transfusions (OR = 2.66; 95% CI, 1.20-5.89), frequent medical injections (OR = 2.64; 95% CI, 1.62-4.31), or injections by non-licensed medical providers (OR = 1.91; 95% CI, 1.18-3.09). Multiple logistic regression analysis showed that the significant factors for anti-HCV(+) patients vs. HBsAg(+) patients are drinking habit (OR = 3.45; 95% CI, 1.02-11.60), age (OR = 6.33; 95% CI, 2.93-13.68), and frequent medical injections (OR = 2.88; 95% CI, 1.65-5.03). The transmission of hepatitis C in A-Lein is closely related to low socioeconomic status, age, alcohol abuse, spouses being anti-HCV(+), and frequent medical injections, especially from non-licensed medical providers, including both pharmacists and those with no medical licensing whatsoever. These nonlicensed medical providers sometimes reuse needles to save money, which is a likely route of infection.     

Economic analysis and optimization of tool portfolio in semiconductor manufacturing

The tool portfolio of a plant refers to the makeup, in quantity and type, of processing machines in the plant. It is determined by taking into consideration the future trends of process and machine technologies and the forecasts of product evolution and product demands. Portfolio planning is also a multicriteria decision-making task involving tradeoffs among, investment cost, throughput, cycle time, and risk. Tool portfolio planning is a complex task that has strong bearing on manufacturing efficiency. In the first part of this paper, a multicriteria economic decision model is presented for optimal configuration. of the portfolio and to determine the optimal factory loading. The second and third parts of the paper contain applications of the model. If plants are closely located or have a twin-plant design, portfolio planning at multiple plants can be integrated to enhance the overall effectiveness of portfolios. In the second part, a novel methodology for arbitrating capacity backup between plants is described. Because the economic model is constructed upon a valuation of both cycle time and throughput, it is a suitable method for the evaluation of cycle time reduction projects. The application procedure is outlined in the third part.     

Reliability assessment for solders with a stress buffer layer using ball shear strength test and board-level finite element analysis

The stress buffer layer (SBL) is a widely applied improvement in many advanced packages used to release the stress concentration at solder joints. However, it has been generally found that the metal line adjacent to the SBL may suffer larger deformation and its reliability should be addressed. In this study, the panel level package (PLP) technology with solder on polymer (SOP) structure is selected as the testing sample to investigate the effect of SBL. The ball shear strength test is conducted first to investigate the reliability of metal trace in PLP. In addition, finite element (FE) analysis is applied to understand the actual thermo-mechanical behavior of PLP after its assembly. The package-level and board-level reliability assessments are compared, and the suggested layout of the redistribution layer on the SBL is provided herein.     

Effects of hot carrier induced interface state generation insubmicron LDD MOSFET's

A two-dimensional numerical simulation including a new interface state generation model has been developed to study the performance variation of a LDD MOSFET after a dc voltage stress. The spatial distribution of hot carrier induced interface states is calculated with a breaking silicon-hydrogen bond model. Mobility degradation and reduction of conduction charge due to interface traps are considered. A 0.6 μm LDD MOSFET was fabricated. The drain current degradation and the substrate current variation after a stress were characterized to compare the simulation. A reduction of the substrate current at V_g ≃0.5 V_d in a stressed device was observed from both the measurement and the simulation. Our study reveals that the reduction is attributed to a distance between a maximum channel electric field and generated interface states     

Low RF noise and power loss for ion-implanted Si having an improved implantation process

Very-low-transmission line noise of <0.25 dB at 18 GHz and low power loss /spl les/0.6 dB at 110 GHz have been measured on transmission lines fabricated on proton-implanted Si. In contrast, a standard Si substrate gave much higher noise of 2.5 dB and worse power loss of 5 dB. The good RF integrity of proton-implanted Si results from the high isolation impedance to ground, as analyzed by an equivalent circuit model. The proton implantation is also done after forming the transmission lines at a reduced implantation energy of /spl sim/4 MeV. This enables easier process integration into current VLSI technology.     

A comparison of lightness contrast effects in CRT and surface colours

The simultaneous contrast effect is investigated in this article. A total of 174 and 154 test/induction combinations were studied for CRT and surface colours respectively. Each combination was assessed by nine observers using a matching technique. The test and induction colours used for CRT colours were similar to surface colours using fabric samples. The results indicated a strong lightness contrast effect for both CRT and surface media; that is, the lightness of a test colour surrounded by a lighter induction colour was reduced for both CRT and surface colours. However, the effect in CRT medium was more pronounced than in the surface medium. © 2004 Wiley Periodicals, Inc. Col Res Appl, 30, 13–20, 2005; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/col.20074