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1.
Kris J. Kozaczek M.Sc. Clayton O. Ruud Ph.D. Joseph C. Conway Jr. Ph.D. Chin-Jye Yu B.S. Ph.D. 《JOM Journal of the Minerals, Metals and Materials Society》1990,42(5):35-38
An advanced x-ray diffraction technique allows the development of texture components to be monitored and provides supplementary information about the cold work and residual stresses in cold-rolled copper sheet. The new technique confirms the results of an ultrasonic test, except for the ultrasonic test’s sensitivity to grain size. The new x-ray diffraction technique could be adapted to provide in-process, nondestructive evaluation of thin copper sheet, even for material moving at high speeds. 相似文献
2.
Chung JY Lee SJ Kris Y Braunschweig T Traicoff JL Hewitt SM 《Proteomics. Clinical applications》2008,2(10-11):1539-1547
Proteomic analysis of formalin-fixed paraffin-embedded (FFPE) tissue offers significant diagnostic utility but is complicated due to the high level of covalently crosslinked proteins arising from formalin fixation. To address these challenges, we developed a reliable protein extraction method for FFPE tissue, based on heat-induced antigen retrieval within a pressure cooker. The protein extraction yield from archival FFPE tissue section is approximately 90% of that recovered from frozen tissue. This method demonstrates preservation of immunoreactivity and recovery of full-length proteins by Western blotting. Additionally, we developed a well-based RP protein array platform utilizing an electrochemiluminescence detection system. Protein samples derived from FFPE tissue by means of laser capture dissection, with as few as 500 shots demonstrate measurable signal differences for different proteins. The lysates coated to the array plate, remain stable over 1?month at room temperature. Theses data suggest that this new protein-profiling platform coupled with the protein extraction method can be used for molecular profiling analysis in FFPE tissue, and contribute to the validation and development of biomarkers in clinical studies. 相似文献
3.
Diederik Verkest Julio Leao Da Silva Jr. Chantal Ykman Kris Croes Miguel Miranda Sven Wuytack Francky Catthoor Gjalt De Jong Hugo De Man 《The Journal of VLSI Signal Processing》1999,21(3):185-194
MATISSE is a design environment intended for developing systems characterized by a tight interaction between control and data-flow behavior, intensive data storage and transfer, and stringent real-time requirements. Matisse bridges the gap from a system specification, using a concurrent object-oriented language, to an optimized embedded single-chip hardware/software implementation. Matisse supports stepwise exploration and refinement of dynamic memory management, memory architecture exploration, and gradual incorporation of timing constraints before going to traditional tools for hardware synthesis, software compilation, and inter-processor communication synthesis. With this approach, specifications of embedded systems can be written in a high-level programming language using data abstraction. Application of MATISSE on telecom protocol processing systems in the ATM area shows significant improvements in area usage and power consumption. 相似文献
4.
Kris A. Bertness Aric W. Sanders Devin M. Rourke Todd E. Harvey Alexana Roshko John B. Schlager Norman A. Sanford 《Advanced functional materials》2010,20(17):2911-2915
The location of GaN nanowires is controlled with essentially perfect selectivity using patterned SiNx prior to molecular beam epitaxy growth. Nanowire growth is uniform within mask openings and absent on the mask surface for over 95% of the usable area of a 76 mm diameter substrate. The diameters of the resulting nanowires are controlled by the size of the mask openings. Openings of approximately 500 nm or less produce single nanowires with symmetrically faceted tips. 相似文献
5.
Dawson TW Caputa K Stuchly MA Shepard RB Kavet R Sastre A 《IEEE transactions on bio-medical engineering》2002,49(3):254-262
Human exposure to external 50/60-Hz electric and magnetic fields induces electric fields within the body. These induced fields can cause interference with implanted pacemakers. In the case of exposure to magnetic fields, the pacemaker leads are subject to induced electromotive forces, with current return paths being provided by the conducting body tissues. Modern computing resources used in conjunction with millimeter-scale human body conductivity models make numerical modeling a viable technique for examining any such interference. In this paper, an existing well-verified scalar-potential finite-difference frequency-domain code is modified to handle thin conducting wires embedded in the body. The effects of each wire can be included numerically by a simple modification to the existing code. Results are computed for two pacemaker lead insertion paths, terminating at either atrial or ventricular electrodes in the heart. Computations are performed for three orthogonal 60-Hz magnetic field orientations. Comparison with simplified estimates from Faraday's law applied directly to extracorporeal loops representing unipolar leads underscores problems associated with this simplified approach. Numerically estimated electromagnetic interference (EMI) levels under the worst case scenarios are about 40 microT for atrial electrodes, and 140 microT for ventricular electrodes. These methods could also be applied to studying EMI with other implanted devices such as cardiac defibrillators. 相似文献
6.
Bryan Kris 《世界电子元器件》2008,(10)
市场因素正在推动智能电源的发展,包括电源的外部控制和生产中的软件配置。实现上述目标的方法之一就是在电源转换回路中采用数字反馈控制。电源设计人员已经在智能电源中采用了单片机(MCU)来实现通信、监视、控制和诸如上电时序、软启动和拓扑控制等确定性功能。但是,就在不久前,由于没有合适的兼具成本效率的技术,对电源转换回路进行完全的数字控制仍不可能。 相似文献
7.
Filip Duerinckx Kris Van Nieuwenhuysen Hyonju Kim Izabela Kuzma‐Filipek Harold Dekkers Guy Beaucarne Jef Poortmans 《Progress in Photovoltaics: Research and Applications》2005,13(8):673-690
Thin‐film epitaxial silicon solar cells are an attractive future alternative for bulk silicon solar cells incorporating many of the process advantages of the latter, but on a potentially cheap substrate. Several challenges have to be tackled before this potential can be successfully exploited on a large scale. This paper describes the points of interest and how IMEC aims to solve them. It presents a new step forward towards our final objective: the development of an industrial cell process based on screen‐printing for > 15% efficient epitaxial silicon solar cells on a low‐cost substrate. Included in the discussion are the substrates onto which the epitaxial deposition is done and how work is progressing in several research institutes and universities on the topic of a high‐throughput epitaxial reactor. The industrial screen‐printing process sequence developed at IMEC for these epitaxial silicon solar cells is presented, with emphasis on plasma texturing and improvement of the quality of the epitaxial layer. Efficiencies between 12 and 13% are presented for large‐area (98 cm2) epitaxial layers on highly doped UMG‐Si, off‐spec and reclaim material. Finally, the need for an internal reflection scheme is explained. A realistically achievable internal reflection at the epi/substrate interface of 70% will result in a calculated increase of 3 mA/cm2 in short‐circuit current. An interfacial stack of porous silicon layers (Bragg reflectors) is chosen as a promising candidate and the challenges facing its incorporation between the epitaxial layer and the substrate are presented. Experimental work on this topic is reported and concentrates on the extraction of the internal reflection at the epi/substrate interface from reflectance measurements. Initial results show an internal reflectance between 30 and 60% with a four‐layer porous silicon stack. Resistance measurements for majority carrier flow through these porous silicon stacks are also included and show that no resistance increase is measurable for stacks up to four layers. Copyright © 2005 John Wiley & Sons, Ltd. 相似文献
8.
The IP/MPLS-based ASON/GMPLS hybrid network architecture enables the interaction between the IP layer and the optical dense wavelength division multiplexing (DWDM) layer. This architecture makes it possible to transfer huge amounts of traffic data on DWDM networks, while supporting Internet Protocol (IP)-based service applications. Additionally, this architecture provides a unified routing scenario, which allows the dynamic routing in both the IP layer and/or optical layer. Cross- layer routing has been addressed in single domain networks scenarios, where the routing policies Physical Topology First (PTF) and Virtual Topology First (VTP) have been proposed and applied. However, applying cross-layer routing using both routing topology policies PTF and VTF has not been investigated in a multi-domain networks scenario yet. In this study, we address this issue and propose a routing scheme to establish traffic connections in the optical WDM layer and the IP layer, which makes the applicability of PTF and VTF in multilayer multi-domain network feasible. 相似文献
9.
Wiljan Smaal Charlotte Kjellander Yongbin Jeong Ashutosh Tripathi Bas van der Putten Antonio Facchetti Henry Yan Jordan Quinn John Anthony Kris Myny Wim Dehaene Gerwin Gelinck 《Organic Electronics》2012,13(9):1686-1692
Complementary thin-film transistor circuits composed of 6,13-bis(triisopropyl-silylethynyl) pentacene (TIPS–PEN) and a rylene carboxylic diimide derivative for p- and n-channel thin-film transistors (TFTs) were fabricated on flexible foils. The so-called staggered TFT configuration is used, meaning that the semiconductors layers are deposited last. The work-function of the injecting gold electrodes were modified using several self-assembled monolayers (SAMs). For optimized contacts the mobility of the n- and p-channel TFTs was 0.5 cm2/Vs and 0.2 cm2/Vs, respectively. Strongly degraded performance is obtained when the n-channel material was printed on contacts optimized for the p-channel TFT, and vice versa. This illustrates that for CMOS circuits we need careful work-function engineering to allow proper injection for both electrons and holes. We show for the first time that by using a bimolecular mixture for the SAM we can systematically vary the work function, and demonstrate how this affects the performance of discrete n-type and p-type transistors, as well as CMOS inverters and ring oscillators. Under optimal processing conditions we realized complementary 19-stage ring oscillators with 10 μs stage delay operating at 20 V. 相似文献
10.
Christen K 《Environmental science & technology》2005,39(3):59A-60A