Survey of dirofilariasis in Arkansas

A card survey was sent to 340 veterinarians in the Urban, Delta, Highland and Coastal Plain regions of Arkansas. Veterinarians were asked to indicate numbers of dogs tested, confirmed Dirofilaria immitis positive, diagnostic techniques, frequency and period tested. A significantly greater percentage of dogs tested D. immitis positive in the Delta region as compared with the Urban region. There were no significant differences in the percentage of treated dogs on prophylaxis or the types of diagnostic tests among regions.     

A Multistage Architecture for Statistical Inference with Stochastic Signal Acquisition

We describe a statistical inference approach for designing signal acquisition interfaces and inference systems with stochastic devices. A signal is observed by an array of binary comparison sensors, such as highly scaled comparators in an analog-to-digital converter, that exhibit random offsets in their reference levels due to process variations or other uncertainties. These offsets can limit the performance of conventional measurement devices. In our approach, we build redundancy into the sensor array and use statistical estimation techniques to account for uncertainty in the observations and produce a more reliable estimate of the acquired signal. We develop an observational model and find a Cramér-Rao lower bound on the achievable square error performance of such a system. We then propose a two-stage inference architecture that uses a coarse estimate to select a subset of the sensor outputs for further processing, reducing the overall complexity of the system while achieving near-optimal performance. The performance of the architecture is demonstrated using a simulated prototype for parameter estimation and symbol detection applications. The results suggest the feasibility of using unreliable components to build reliable signal acquisition and inference systems.     

Universal linear least squares prediction: upper and lower bounds

We consider the problem of sequential linear prediction of real-valued sequences under the square-error loss function. For this problem, a prediction algorithm has been demonstrated whose accumulated squared prediction error, for every bounded sequence, is asymptotically as small as the best fixed linear predictor for that sequence, taken from the class of all linear predictors of a given order p. The redundancy, or excess prediction error above that of the best predictor for that sequence, is upper-bounded by A/sup 2/P ln(n)/n, where n is the data length and the sequence is assumed to be bounded by some A. We provide an alternative proof of this result by connecting it with universal probability assignment. We then show that this predictor is optimal in a min-max sense, by deriving a corresponding lower bound, such that no sequential predictor can ever do better than a redundancy of A/sup 2/p ln(n)/n.     

Minimum mean squared error equalization using a priori information

A number of important advances have been made in the area of joint equalization and decoding of data transmitted over intersymbol interference (ISI) channels. Turbo equalization is an iterative approach to this problem, in which a maximum a posteriori probability (MAP) equalizer and a MAP decoder exchange soft information in the form of prior probabilities over the transmitted symbols. A number of reduced-complexity methods for turbo equalization have been introduced in which MAP equalization is replaced with suboptimal, low-complexity approaches. We explore a number of low-complexity soft-input/soft-output (SISO) equalization algorithms based on the minimum mean square error (MMSE) criterion. This includes the extension of existing approaches to general signal constellations and the derivation of a novel approach requiring less complexity than the MMSE-optimal solution. All approaches are qualitatively analyzed by observing the mean-square error averaged over a sequence of equalized data. We show that for the turbo equalization application, the MMSE-based SISO equalizers perform well compared with a MAP equalizer while providing a tremendous complexity reduction     

The application of loss-free resistors in power processing circuits

Applications of loss-free elements with resistive characteristics in power processing systems are discussed. The synthesis of this kind of element is based on the control of a two port which has a transformer or gyrator matrix. Both of the controlled two ports can be realized by means of switched mode circuits. The loss-free resistor can be applied to the stabilization of unstable systems, for damping oscillatory waveforms, and balancing of power flow in AC-DC conversion systems. This kind of element has been applied to the stabilization of a gas laser system. It replaced a conventional resistive element which was applied for this purpose     

利用参数DFM减少栅泄漏

初创公司Blaze DFM最近开发的技术大大缩小了设计和生产间的差距。据称公司刚刚推出的软件是业内第一个电可制造设计（DFM）的解决方案。由于是为芯片设计者编写的软件，能够分析设计中怎样应用每个晶体管，并允许选择修正CD减少泄漏电流或优化定时及使泄漏的变化更小。在90到65nm的设计中，已证实此方法可减少泄漏功率40％，泄漏变化60％，定时提高可达10％。     

NEC开发出新型硅纳米光电技术

NEC Corp．日前宣布已成功地开发出基础硅纳米光电技术,消除了数据传输的瓶颈从而推动了光数据在大规模集成(LSI)芯片中的传输。此项研究是在今年年初举行的国际固态电路会议(ISSCC)上提出来的。     

Microlens lithography: A new approach for large display fabrication

Microlens lithography is a new lithographic method, that uses microlens arrays to image a lithographic mask onto a substrate layer. Microlens lithography provides photolithography at a moderate resolution for an almost unlimited area. The imaging system consists of stacked microlens arrays forming an array of micro-objectives. Each micro-objective images a small part of the mask pattern, the images overlap in the image plane. Potential applications for microlens lithography are the fabrication of large area flat panel displays (FPD), color filters, and micromechanics.     

Area-efficient high-throughput MAP decoder architectures

Iterative decoders such as turbo decoders have become integral components of modern broadband communication systems because of their ability to provide substantial coding gains. A key computational kernel in iterative decoders is the maximum a posteriori probability (MAP) decoder. The MAP decoder is recursive and complex, which makes high-speed implementations extremely difficult to realize. In this paper, we present block-interleaved pipelining (BIP) as a new high-throughput technique for MAP decoders. An area-efficient symbol-based BIP MAP decoder architecture is proposed by combining BIP with the well-known look-ahead computation. These architectures are compared with conventional parallel architectures in terms of speed-up, memory and logic complexity, and area. Compared to the parallel architecture, the BIP architecture provides the same speed-up with a reduction in logic complexity by a factor of M, where M is the level of parallelism. The symbol-based architecture provides a speed-up in the range from 1 to 2 with a logic complexity that grows exponentially with M and a state metric storage requirement that is reduced by a factor of M as compared to a parallel architecture. The symbol-based BIP architecture provides speed-up in the range M to 2M with an exponentially higher logic complexity and a reduced memory complexity compared to a parallel architecture. These high-throughput architectures are synthesized in a 2.5-V 0.25-/spl mu/m CMOS standard cell library and post-layout simulations are conducted. For turbo decoder applications, we find that the BIP architecture provides a throughput gain of 1.96 at the cost of 63% area overhead. For turbo equalizer applications, the symbol-based BIP architecture enables us to achieve a throughput gain of 1.79 with an area savings of 25%.