N-Type Field-Effect Transistors Using Multiple Mg-Doped ZnO Nanorods

Nanorod field-effect transistors (FETs) that use multiple Mg-doped ZnO nanorods and a SiO₂ gate insulator were fabricated and characterized. The use of multiple nanorods provides higher on-currents without significant degradation in threshold voltage shift and subthreshold slopes. It has been observed that the on-currents of the multiple ZnO nanorod FETs increase approximately linearly with the number of nanorods, with on-currents of ~1 muA per nanorod and little change in off-current (~4times10^-12). The subthreshold slopes and on-off ratios typically improve as the number of nanorods within the device channel is increased, reflecting good uniformity of properties from nanorod to nanorod. It is expected that Mg dopants contribute to high n-type semiconductor characteristics during ZnO nanorod growth. For comparison, nonintentionally doped ZnO nanorod FETs are fabricated, and show low conductivity to compare with Mg-doped ZnO nanorods. In addition, temperature-dependent current-voltage characteristics of single ZnO nanorod FETs indicate that the activation energy of the drain current is very low (0.05-0.16 eV) at gate voltages both above and below threshold     

SO2 SCRUBBING BY ULTRAFINE CA(OH)2 AEROSOL

The objective of the present study was to generate submicrometer calcium hydroxide aerosols and to investigate the effectiveness of such aerosols in sulfur capture. The effectiveness of SO₂ removal by Ca(OH)₂ aerosol has been investigated in an isothermal reactor. Ca(OH) ₂ aerosol was generated by a novel fluidizer system in which submicrometer-sized powders were entrained in gases. SO₂ was added to this aerosol to a concentration of 2000 ppm. The aerosol-SO₂ mixture was heated to 550°C-750°C in an isothermal tube reactor. The SO₂ removal efficiency, which varied from 20% to 70%, was determined to be a function of the aerosol concentration, reactor temperature and residence time. The fraction of aerosol reacted was not affected strongly by the aerosol concentration. The reaction kinetics were determined from the experimental data using a simple analytical model in which the rate is first order in both SO₂ and calcium hydroxide aerosol concentrations.     

Effect of structure on the thermal behaviour of ethynyl-terminated imide resins

A series of ethynyl-terminated aromatic imide monomers containing phosphine oxide in the backbone were synthesized by the reaction of tris(3-aminophenyl) phosphine oxide (TAP) or bis(3-aminophenyl)methyl phosphine oxide (BAP) with pyromellitic dianhydride (PMDA) or 3, 3′,4, 4′-benzophenone tetracarboxylic acid dianhydride (BTDA) or 4, 4′-perfluoroisopropylidenebis(phthalic anhydride), and 3-ethynyl aniline. Structural characterization was done by infrared, nuclear magnetic resonance spectroscopy and elemental analysis. Thermal characterization was done by differential scanning calorimetry and thermogravimetric analysis. The decomposition temperatures of cured resins were above 500°C in nitrogen atmosphere. Char yield at 800°C ranged from 52–63.5%.     

Synthesis and Anti-Cancer Activity of New Pyrazolinyl-Indole Derivatives: Pharmacophoric Interactions and Docking Studies for Identifying New EGFR Inhibitors

Newly designed series of indole-containing pyrazole analogs, pyrazolinylindoles, were synthesized, and their structures were confirmed based on the spectral data of the ¹H NMR, ¹³C NMR, and HR-MS analyses. Preliminary anti-cancer activity testings were carried out by the National Cancer Institute, United States of America (NCI, USA). Compounds HD02, HD05, and HD12 demonstrated remarkable cytotoxic activities against nine categories of cancer types based cell line panels which included leukemia, colon, breast, melanoma, lungs, renal, prostate, CNS, and ovarian cancer cell lines. The highest cytotoxic effects were exhibited by the compounds HD02 [1-(5-(1-H-indol-3-yl)-3-(p-tolyl)-4,5-dihydro-1H-pyrazol-1-yl)-2-phenylethanone], HD05 [1-(3-(4-chlorophenyl)-5-(1H-indol-3-yl)-4,5-dihydro-1H-pyrazol-1-yl)-2-phenoxyethanone], and HD12 [(3-(4-chlorophenyl)-5-(1H-indol-3-yl)-4,5-dihydro-1H-pyrazol-1-yl)(pyridin-4-yl)methanone] against some of the 56 types of NCI-based cell lines in different panels. Compound HD05 showed the maximum range of cancer cell growth inhibitions against all categories of the cell lines in all nine panels. On average, in comparison to the referral standard, imatinib, at a dose level of 10 µM, the HD05 showed significant activity against leukemia in the range of 78.76%, as compared to the imatinib at 9% of cancer cells’ growth inhibitions. Molecular docking simulation studies were performed in silico on the epidermal growth factor receptor (EGFR) tyrosine kinase, in order to validate the activity.     

Maximum error modeling for fault-tolerant computation using maximum a posteriori (MAP) hypothesis

The application of current generation computing machines in safety-centric applications like implantable biomedical chips and automobile safety has immensely increased the need for reviewing the worst-case error behavior of computing devices for fault-tolerant computation. In this work, we propose an exact probabilistic error model that can compute the maximum error over all possible input space in a circuit-specific manner and can handle various types of structural dependencies in the circuit. We also provide the worst-case input vector, which has the highest probability to generate an erroneous output, for any given logic circuit. We also present a study of circuit-specific error bounds for fault-tolerant computation in heterogeneous circuits using the maximum error computed for each circuit. We model the error estimation problem as a maximum a posteriori (MAP) estimate [28] and [29], over the joint error probability function of the entire circuit, calculated efficiently through an intelligent search of the entire input space using probabilistic traversal of a binary Join tree using Shenoy-Shafer algorithm [20] and [21]. We demonstrate this model using MCNC and ISCAS benchmark circuits and validate it using an equivalent HSpice model. Both results yield the same worst-case input vectors and the highest percentage difference of our error model over HSpice is just 1.23%. We observe that the maximum error probabilities are significantly larger than the average error probabilities, and provides a much tighter error bounds for fault-tolerant computation. We also find that the error estimates depend on the specific circuit structure and the maximum error probabilities are sensitive to the individual gate failure probabilities.     

In-Flight Synthesis of Core–Shell Mg/Si–SiOx Particles with Greatly Reduced Ignition Temperature

Magnesium is a promising candidate as a solid fuel for energetic applications, however, the diffusion-controlled oxidation mechanism impedes its reaction with an oxidizer, often resulting in diminished performance. In this study, non-thermal plasma processing is implemented to modify the surface of magnesium nanoparticles with silicon in-flight, in the gas-phase to enhance the rate of interfacial reactions and tune the ignition pathways. Allowing the silicon coating to partially oxidize provides direct contact between the fuel and oxidizer, resulting in a nanostructured thermite system at the single particle level. The proximal distance between oxidizer and fuel directly impacts the ignition temperature and, therefore, the combustion kinetics. An intermetallic reaction occurs within the magnesium/silicon system to supplement the heating of the magnesium fuel to initiate its reaction with the oxidizer, resulting in highly reduced ignition thresholds. The ignition temperature is lowered significantly from ≈740 °C for magnesium particles with a native oxide layer to ≈520 °C for particles coated via the in-flight plasma process.     

Modelling methodology for thermal analysis of hot solder dip process

The shift of electronics industry towards the use of lead-free solders in components manufacturing brought also the challenge of addressing the problem of tin whiskers. Manufacturers of high reliability and safety critical equipment in sectors such as defence and aerospace rely increasingly on the use of commercial-of-the-shelf (COTS) electronic components for their products and systems. The use of COTS components with lead-free solder plated terminations comes with the risks for their long term reliability associated with tin whisker growth related failures. In the case of leaded type electronic components such as Quad Flat Package (QFP) and Small Outline Package (SOP), one of the promising solutions to this problem is to “re-finish” the package terminations by replacing the lead-free solder coatings on the leads with conventional tin–lead solder. This involves subjecting the electronic components to a post-manufacturing process known as Hot Solder Dip (HSD). One of the main concerns for adopting HSD (refinishing) as a strategy to the tin whisker problem is the potential risk for thermally induced damage in the components when subjected to this process.     

Numerical study on thermal impacts of different void patterns on performance of chip-scale packaged power device

Chip scale package (CSP) technology offers promising solutions to package power device due to its relatively good thermal performance among other factors. Solder thermal interface materials (STIMs) are often employed at the die bond layer of a chip-scale packaged power device to enhance heat transfer from the chip to the heat spreader. Nonetheless, the presence of voids in the solder die-attach layer impedes heat flow and could lead to an increase in the peak temperature of the chip. Such voids which form easily in the solder joint during reflow soldering process at manufacturing stage are primarily occasioned by out-gassing phenomenon and defective metallisation. Apparently, the thermal consequences of voids have been extensively studied, but not much information exist on precise effects of different patterns of solder die-attach voids on the thermal performance of chip-level packaged power device. In this study, three-dimensional finite element analysis (FEA) is employed to investigate such effects. Numerical studies were carried out to characterise the thermal impacts of various voids configurations, voids depth and voids location on package thermal resistance and chip junction temperature. The results show that for equivalent voiding percentage, thermal resistance increases more for large coalesced void type in comparison to the small distributed voids configuration. In addition, the study suggests that void extending through the entire thickness of solder layer and voids formed very close to the heat generating area of the chip can significantly increase package thermal resistance and chip junction temperature. The findings of this study indicate that void configurations, void depth and void location are vital parameters in evaluating the thermal effects of voids.     

Efficient Computation Offloading Decision in Mobile Cloud Computing over 5G Network

Due to the significant advancement of Smartphone technology, the applications targeted for these devices are getting more and more complex and demanding of high power and resources. Mobile cloud computing (MCC) allows the Smart phones to perform these highly demanding tasks with the help of powerful cloud servers. However, to decide whether a given part of an application is cost-effective to execute in local mobile device or in the cloud server is a difficult problem in MCC. It is due to the trade-off between saving energy consumption while maintaining the strict latency requirements of applications. Currently, 5th generation mobile network (5G) is getting much attention, which can support increased network capacity, high data rate and low latency and can pave the way for solving the computation offloading problem in MCC. In this paper, we design an intelligent computation offloading system that takes tradeoff decisions for code offloading from a mobile device to cloud server over the 5G network. We develop a metric for tradeoff decision making that can maximize energy saving while maintain strict latency requirements of user applications in the 5G system. We evaluate the performances of the proposed system in a test-bed implementation, and the results show that it outperforms the state-of-the-art methods in terms of accuracy, computation and energy saving.