Oxidation of some aliphatic polyols on anodically deposited MnO2

Galvanostatic steady state current potential measurements were carried out for oxidation of a series of aliphatic alcohols having varying number of hydroxyl groups. The anodically deposited layer of MnO₂ on platinum was used as the electrode material. The deposit was characterised by scanning electron microscopy (SEM), energy dispersive X-ray analysis (EDAX) and electrode potential measurements. The catalytic role of MnO₂ in the electro-oxidation of alcohols was indicated by the chronopotentiograms and the cyclic voltammograms. An analysis of the electrochemical data indicated a catalytic EC mechanism in which Mn (V) is generated electrochemically and consumed chemically in succession. Based on this and the hydrogen bonding interaction between alcoholic hydroxyl groups and MnO₂ layer, a mechanism was proposed which accounts for the variation in the observed electrochemical reaction orders. Tafel behaviour was found to be followed only approximately. Current efficiency of the electrochemical oxidation of polyols was studied. Replacement of platinum by carbon as current collector was found to leave the electrocatalytic activity of the MnO₂ deposit practically unaltered.     

Crosstalk analysis for a CMOS gate driven inductively and capacitively coupled interconnects

This paper deals with crosstalk analysis of a CMOS driven capacitively and inductively coupled interconnect. The Alpha Power Law model of MOS transistor is used to represent a CMOS driver. This is combined with a transmission line-based coupled RLC model of interconnect to develop a composite model for analytical purpose. On this basis a transient analysis of crosstalk noise is carried out. Comparison of the analytical results with SPICE extracted results shows that the error involved is nominal.     

Visual Speech Recognition Using Optical Flow and Hidden Markov Model

Wireless Personal Communications - The present work proposes audio-visual speech recognition with the use of Gammatone frequency cepstral coefficient (GFCC) and optical flow (OF) features with...     

Simulation model for sizing of stand-alone solar PV system with interconnected array

Solar PV arrays made of interconnected modules are comparatively less susceptible to shadow problem and power degradation resulting from the aging of solar cells. This paper presents a simulation model for the sizing of stand-alone solar PV systems with interconnected arrays. It considers the electricity generation in the array and its storage in the battery bank serving the fluctuating load demand. The loss of power supply probability (LPSP) is used to connote the risk of not satisfying the load demand. The non-tracking (e.g., fixed and tilted) and single-axis tracking aperture arrays having cross-connected modules of single crystalline silicon solar cells in a (6×6) modular configuration are considered. The simulation results are illustrated with the help of a numerical example wherein the load demand is assumed to follow uniform probabilistic distribution. For a given load, the numbers of solar PV modules and batteries corresponding to zero values of LPSP on diurnal basis during the year round cycle of operation are presented. The results corresponding to the surplus and deficit of energy as a function of LPSP are also presented and discussed to assess the engineering design trade offs in the system components.Furthermore, a simple cost analysis has also been carried out, which indicates that for Delhi the stand-alone solar PV systems with fixed and tilted aperture arrays are better option than those with single-axis tracking aperture (with north–south oriented tracking axis) arrays.     

Tokens vs. Signals: On Conformance between Formal Models of Dataflow and Hardware

Designing hardware often involves several types of modeling and analysis, e.g., in order to check system correctness, to derive performance properties such as throughput, to optimize resource usages (e.g., buffer sizes), and to synthesize parts of a circuit (e.g., control logic). Working directly with low-level hardware models such as finite-state machines (FSMs) to answer such questions is often infeasible, e.g., due to state explosion. Instead, designers often use dataflow models such as SDF and CSDF, which are more abstract than FSMs, and less expensive to use since they come with more efficient analysis algorithms. However, dataflow models are only abstractions of the real hardware, and often omit critical information. This raises the question, when can one say that a certain dataflow model faithfully captures a given piece of hardware? The question is of more than simply academic interest. Indeed, as illustrated in this paper, dataflow-based analysis outcomes may sometimes be defensive (e.g., buffers that are too big) or even incorrect (e.g., buffers that are too small). To answer the question of faithfully capturing hardware using dataflow models, we develop a formal conformance relation between the heterogeneous formalisms of (1) finite-state machines with synchronous semantics, typically used to model synchronous hardware, and (2) asynchronous processes communicating via queues, used as a formal model for dataflow. The conformance relation preserves performance properties such as worst-case throughput and latency.     

A 4-MB on-chip L2 cache for a 90-nm 1.6-GHz 64-bit microprocessor

A 4-MB L2 data cache was implemented for a 64-bit 1.6-GHz SPARC(r) RISC microprocessor. Static sense amplifiers were used in the SRAM arrays and for global data repeaters, resulting in robust and flexible timing operation. Elimination of the global clock grid over the SRAM array saves power, enabled by combining the clock information with array select signals. Redundancy was implemented flexibly, with shift circuits outside the main data array for area efficiency. The chip integrates 315 million transistors and uses an 8-metal-layer 90-nm CMOS process.     

Generation of square and triangular wave with independently controllable frequency and amplitude using OTAs only and its application in PWM

This paper presents a self-generating square/triangular wave generator using only the CMOS Operational Transconductance Amplifiers (OTAs) and a grounded capacitor. The output frequency and amplitude of the proposed circuit can be independently and electronically adjusted. The proposed circuit validates its advantage by consuming less amount of power, which is about 71.3 µW. The theoretical aspects are authentically showcased using the PSPICE simulation results. The performance of the proposed circuit is also verified through pre layout and post layout simulation results using the 90 nm GPDK CMOS parameters. A prototype of this circuit has been made using commercially available IC CA3080 for experimental verification. Experimentation also gives the similar output as per the theoretical proposition. The designed circuit is also made applicable to perform pulse width modulation (PWM).     

Potential remedies for the VT/Vfb-shift problem of Hf/polysilicon-based gate stacks: a solution-based survey

In this paper, we report on several different approaches that were implemented on both capacitor and scaled planar MOS transistor devices in order to prevent or undo the commonly observed V_T/V_fb-shift and –instability for Hf-based high-κ gate stacks in conjunction with a poly-Si electrode. While the latter issue can eventually be mitigated, the V_T-shift problem jeopardizes initial high-κ integration with poly-Si for the 65 nm and also for the 45 nm node. The different attempts to circumvent this problem include (1) bulk modifications of the high-κ stack/process, (2) the use of various thin capping layers at the poly/high-κ interface and (3) chemical and process modifications of the gate electrode deposition. We have observed that, although considerable improvements have been made in terms of e.g. yield, performance and instability, none of these techniques succeeded in obtaining V_T-values in line with the ITRS device specifications, i.e. avoiding Fermi Level Pinning to occur for poly-Si/Hf(Si)O(N) stacks.