五步创造有效的规划

<正> 对一个团队和组织来说,创造一个有效的规划是最具挑战性的任务之一。规划在这里不是指几个简单的句子,而是一种对未来状态的彻底的清晰认识,它包括对价值观、步骤、结构、技术、工作角色和环境的明确认识。但问题是:需要采取什么样的步骤才能为自己的组织创造一个有效和可行的规划呢?本文介绍的模块提供了一些基本的步骤,它们能大大提高创造一个有效的规划的可能性。     

News: White House panel creating database of endocrine disrupter-related research

Science.     

Influence of Amorphous Grain Boundary Phases on the Superplastic Behavior of 3-mol%-Yttria-Stabilized Tetragonal Zirconia Polycrystals (3Y-TZP)

Amorphous silicate grain boundary phases of varying chemistry and amounts were added to 3Y-TZP in order to determine their influence on the superplastic behavior between 1200° and 1300°C and on the room-temperature mechanical properties. Strain rate enhancement at high temperatures was observed in 3Y-TZP containing a glassy grain boundary phase, even with as little as 0.1 wt% glass. Strain rate enhancement was greatest in 3Y-TZP with 5 wt% glass, but the room-temperature hardness, elastic modulus, and fracture toughness were degraded. The addition of glassy grain boundary phases did not significantly affect the stress exponent of 3Y-TZP, but did lower the activation energy for superplastic flow. Strain rate enhancement was highest in samples containing the grain boundary phase with the highest solubility for Y₂O₃ and ZrO₂, but the strain rate did not scale inversely with the viscosity of the silicate phases. Grain boundary sliding accommodated by diffusional creep controlled by an interface reaction is proposed as the mechanism for superplastic deformation in 3Y-TZP with and without glassy grain boundary phases.     

Global Interoperability Using Semantics, Standards, Science and Technology (GIST)

“Global Interoperability Using Semantics, Standards, Science and Technology” is a concept that is predicated on the assumption that the semantic integration, frameworks and standards that support information exchange, and advances in science and technology can enable information-systems interoperability for many diverse users. This paper recommends technologies and approaches for enabling interoperability across a wide spectrum of political, geographical, and organizational levels, e.g. coalition, federal, state, tribal, regional, non government, and private. These recommendations represent steps toward the goal of the Semantic Web, where computers understand information on web sites through knowledge representations, agents, and ontologies.     

用于精确焊接的智能视觉系统

通过与其它传感技术的对比,简要分析了激光视觉在焊接生产中得到成功应用的原因。分析了早期激光视觉系统的特征和当时面临的挑战。介绍了Servo-Robot激光视觉的关键技术和已取得的显著进步,阐述了集成激光视觉的移动式便携焊接机器人和激光视觉在焊缝质量检测中的应用。展望了激光视觉系统的未来和智能视觉在提高机器人性能方面发展的显著进步,包括改进机器人人工示教、离线编程及视觉辅助机器人示教。     

Technologies and the development of the Automated Metadata Indexing and Analysis (AMIA) system

The Automated Metadata Indexing and Analysis (AMIA) project aims to provide an effective digital asset management (DAM) tool for large digital asset databases. We began with text-based indexing since it is still the most reliable approach as compared with other content-based media features. AMIA not only searches for the text of the file name, but also utilizes embedded information such as the metadata in Maya files. The AMIA system builds a linked map between all dependency files. We present an approach of preserving previously established metadata created by the old DAM tools, such as AlienBrain, and integrating them into the new system. Findings indicate that AMIA has significantly improved search performance comparing to previous DAM tools. Finally, the ongoing and future work in the AMIA project is described.     

Low-Power Parallel Video Compression Architecture for a Single-Chip Digital CMOS Camera

A low-power, large-scale parallel video compression architecture for a single-chip digital CMOS camera is discussed in this paper. This architecture is designed for highly computationally intensive image and video processing tasks necessary to support video compression. Two designs of this architecture, an MPEG2 encoder and a DV encoder, are presented. At an image resolution of 640 × 480 pixels (MPEG2) and 720 × 576 (DV) and a frame rate of 25 to 30 frames per second, a computational throughput of up to 1.8 billion operations per second (BOPS) is required. This is supported in the proposed architecture using a 40 MHz clock and an array of 40 to 45 parallel processors implemented in a 0.2 m CMOS technology and with a 1.5 V supply voltage. Power consumption is significantly reduced through the single-chip integration of the CMOS photo sensors, the embedded DRAM technology, and the proposed pipelined parallel processors. The parallel processors consume approximately 45 mW of power resulting a power efficiency of 40 BOPS/W.