一种数字CMOS工艺制造的10位100MS/s流水线ADC

介绍了采用0.18μm数字工艺制造、工作在3.3V下、10位100MS/s转换速率的流水线模数转换器。提出了一种适用于1.5位MDAC的新的金属电容结构,并且使用了高带宽低功耗运算放大器、对称自举开关和体切换的PMOS开关来提高电路性能。芯片已经通过流片验证,版图面积为1.35mm×0.99mm,功耗为175mW。14.7MS/s转换速率下测得的DNL和INL分别为0.2LSB和0.45LSB,100MS/s转换速率下测得的DNL和INL分别为1LSB和2.7LSB,SINAD为49.4dB,SFDR为66.8dB。     

用于便携式健康监护设备的低功耗、低噪声模拟前端电路

本文介绍的用于处理人体生物电信号的模拟前端电路包括仪表放大器、滤波器和可变增益、带宽放大器。仪表放大器采用电容耦合输入来消除直流电极失调。基于电流反馈拓扑结构的IA通过在输入和反馈网络中采用电容分压器来降低功耗。并且,仪表放大器的输入差分对采用互补CMOS输入来提高输入跨导以减小等效输入热噪声。该电路采用Global Foundry 0.35微米 CMOS 工艺流片,电路消耗的总电流为3.96uA,电源电压为3.3V。测试得到的等效输入噪声是0.85uVrms(0.5-100Hz), 噪声能效因子值为6.48。     

一个低功耗的带片上参考电压缓冲器的12位30兆采样率的CMOS流水线模数转换器

介绍了一个在0.13µm 1P8M CMOS工艺下实现的12位30兆采样率流水线模数转换器。提出了一种消除前端采样保持电路的低功耗设计方法。除了第一级之外,带双输入的两级cascode补偿的运算放大器在相邻级间共享以进一步地减小功耗。该模数转换器在5MHz的模拟输入和30.7MHz的采样速率下达到了65.3dB的SNR,75.8dB的SFDR和64.6dB的SNDR。该芯片在1.2V电源电压下消耗33.6mW。FOM达到了0.79pJ/conv step。     

A 455 nW 220 fJ/conversion-step 12 bits 2 kS/s SAR ADC for portable biopotential acquisition systems

An ultra-low power 12 bits 2 kS/s successive approximation register analog-to-digital converter(ADC) is presented.For power optimization,the voltage supply of the digital part is lowered,and the offset voltage of the latch is self-calibrated.Targeted for better linearity and lower noise,an improved digital-to-analog converter capacitor array layout strategy is presented,and a low kick-back noise latch is proposed.The chip was fabricated by using 0.18μm 1P6M CMOS technology.The ADC achieves 61.8 dB SNDR and dissipates 455 nW only,resulting in a figure of merit of 220 fJ/conversion-step.The ADC core occupies an active area of only 674×639μm~2.     

A sub-sampling 4-bit 1.056-GS/s flash ADC with a novel track and hold amplifier for an IR-UWB receiver

A sub-sampling 4-bit 1.056-GS/s flash ADC with a novel track and hold amplifier(THA) in 0.13μm CMOS for an impulse radio ultra-wideband(IR-UWB) receiver is presented.The challenge is in implementing a sub-sampling ADC with ultra-high input signal that further exceeds the Nyquist frequency.This paper presents,to our knowledge for the second time,a sub-sampling ADC with input signals above 4 GHz operating at a sampling rate of 1.056 GHz.In this design,a novel THA is proposed to solve the degradation in amplitude and improve the linearity of signal with frequency increasing to giga Hz.A resistive averaging technique is carefully analyzed to relieve noise aliasing.A low-offset latch using a zero-static power dynamic offset cancellation technique is further optimized to realize the requirements of speed,power consumption and noise aliasing.The measurement results reveal that the spurious free dynamic range of the ADC is 30.1 dB even if the input signal is 4.2 GHz sampled at 1.056 GS/s.The core power of the ADC is 30 mW,excluding all of the buffers,and the active area is 0.6 mm~2.The ADC achieves a figure of merit of 3.75 pJ/conversion-step.     

A 0.8–3GHz RF-VGA with 35dB dynamic range in 0.13μm CMOS* Qin Xi(秦希), Huang Xingli(黄杏丽), Qin Yajie(秦亚杰), Hong Zhiliang(洪志良)?

本文提出了一种使用0.13μm CMOS工艺实现的宽带可变增益放大器（VGA）结构。为了优化该VGA的噪声性能,一个具有15dB固定增益、采用有源反馈结构的预放大器被用来作为第一级,之后采用级联的改进型Cherry-Hooper放大器提供增益调节,双反馈环路在这里被用来扩展Cherry-Hooper放大器的带宽。负容性中和和电容源极退化技术分别被用来进行密勒效应补偿和直流失调取消。测试结果显示,该VGA达到35dB增益调节范围,其高端3dB带宽大于3GHz,在最低增益时,1dB压缩点为-29dBm,在最高增益时,噪声系数达到9dB。该VGA（不包括输出缓冲器）在1.2V电源电压下消耗32mW功率,占用芯片面积为0.48mm₂。