Partial oxidation of methane to syngas using NiO‐supported catalysts

Claims for the partial oxidation of methane to CO and H₂ have been clouded by the possibility of the indirect reaction sequence occurring at hot spots in the catalyst bed. In this report, we claim that the direct reaction occurs on NiO/silica at 500°C with methane conversions as high as 80% and selectivities for H₂ of 80% and CO of 70%. Arguments are presented to show that the amount of diluent gas employed prevents formation of local hot spots with temperatures high enough for the indirect reaction to occur. Consequently, this study constitutes one of the most convincing reports for the conversion of CH₄ to syngas by the partial oxidation of methane. The catalyst deactivates in 10 h. Surface studies show coke formation and aggregation of NiO contribute to the loss of activity. This revised version was published online in August 2006 with corrections to the Cover Date.     

A power efficient charge pump circuit configuration for fast locking PLL application

Microsystem Technologies - One of the vital non-linearity issues that exists in a charge pump (CP) circuit is the current mismatch, which does not only reduce efficiency and increases latency, but...     

Passive element free variation aware decision circuit for 40 Gb/s CDR application

The signal integrity metrics such as jitter, noise, peak-to-peak signal swing and power dissipation play a pivotal role in determining the quality of high data rate on-chip wireline communication and a decision circuit is the most vital section of it. This article explores an area efficient 40 Gb/s configuration of passive element free current mode decision module implemented in 90 nm CMOS technology. The simulation using Cadence Virtuoso platform is carried out at a power supply of 1.2 V along with a clock frequency of 40 GHz and pseudo random bit sequence data input of (2⁷ − 1) having 1 ns bit period. The device foot print of entire arrangement is (76 × 23) µm², which reads a power dissipation, delay, PDP, peak-to-peak jitter and RMS jitter of 7.02 mW, 198.1 ps, 1.391 pJ, 58.00 ps and 13.12 ps respectively. Monte Carlo runs with ‘no skew’ and 5% process skew are performed at different corners to prove the robustness of the design. The whole circuit is finally validated at lower technology node like 28 nm UMC.

     

A design approach of higher oscillation VCO made of CS amplifier with varying active load

This article proposes a design approach of common source (CS) amplifier based Voltage Controlled Oscillator (VCO) to derive higher oscillation frequency. The working feature is such that, the active load of CS amplifier is varied to modulate the flow of current based on a bias circuit steered by an external controlled voltage (V_ctrl), which controls the delay of each stage and thereby regulates the oscillation frequency. The circuit is designed and analyzed on Cadence Virtuoso platform at a supply voltage of 1.2 V for 90 nm CMOS to read a device footprint of 0.105 mm², which offers a power burn and frequency of 2.092 mW and 9.21 GHz respectively with a phase noise and output noise of − 137.9 dBc/Hz and − 168.40 dB at 1 MHz offset frequency. To justify the reliability of the circuit we have conducted worst case analysis by considering effect of power delivery network (PDN) and corner variation along with 500 runs of Monte Carlo. The design is also introduced under 28 nm UMC to validate its scalability with technology trends.