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Test Impact on the Overall Die-to-Wafer 3D Stacked IC Cost 总被引:1,自引:1,他引:0
Mottaqiallah Taouil Said Hamdioui Kees Beenakker Erik Jan Marinissen 《Journal of Electronic Testing》2012,28(1):15-25
One of the key challenges in 3D Stacked-ICs (3D-SIC) is to guarantee high product quality at minimal cost. Quality is mostly
determined by the applied tests and cost trade-offs. Testing 3D-SICs is very challenging due to several additional test moments
for the mid-bond stacks, i.e., partially created stacks. The key question that this paper answers is what is the best test
flow to be used in order to optimize the overall cost while realizing the required quality? We first present a framework covering
different test flows for 3D Die-to-Wafer (D2W) stacked ICs. Thereafter, we present a cost model that allows us to evaluate
these test flows. The impact of different test flows on the overall 3D-SIC cost for several die yields and stack sizes are
investigated; a breakdown of the cost into test, manufacturing and packaging cost is also provided. Our simulation results
show that both the test cost and the overall cost in D2W stacking strongly depends on the selected test flow; test flows with
pre-bond and mid-bond stacking tests (performed during the stacking process) show a higher test cost share, but significantly
reduce the overall 3D-SIC cost. 相似文献
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