Lithium Phenolate Complexes with a Pyridine‐Containing Polymer for Solution‐Processable Electron Injection Layers in PLEDs

A series of (vinylphenyl)pyridine‐based polymer binders, PVPh2Py, PVPh3Py, and PVPh4Py, are designed and synthesized and it is found that mixtures of Liq and the polymers exhibit superior electron injection characteristics as ultrathin (1.6 nm) electron injection layer (EIL) films. They are comparable to those of EILs composed only of Liq. The addition of the polymers does not deteriorate the performance of Liq EILs. Additionally, when the EIL thickness is increased from 1.6 nm to 16 nm, the driving voltages increase and the external quantum efficiencies decrease. The increase in the voltage and decrease in the EQE are suppressed in the device with mixed EILs compared to those observed for the device composed of 100 wt% Liq. Furthermore, the position of the nitrogen in the pyridine ring is considered to influence the electron transport properties of the EILs. The mixing PVPh4Py with Liq improves the driving voltage of the fabricated devices, even with a thick mixed EIL. This reduced dependence of the performance of EILs on their thickness will be advantageous for the coating of large areas using solution processes.     

a-SiC:H/SiO2 Laminated Polarization Splitter for the Wavelength Region Longer Than 1.3 μm Prepared by Plasma-Enhanced Chemical Vapor Deposition

A laminated polarization splitter for the wavelength region longer than 1.3 μm is fabricated for the first time. It is composed of a-SiC:H/SiO₂ alternative multilayers prepared by plasma-enhanced chemical vapor deposition. Splitting behavior is also verified experimentally. It has low absorption loss even for the wavelength region around λ = 1.3 μm because the band-gap energy of a-Sic is larger than that of a-Si. The measured splitting angle is 13.8°, which is 2.4 times larger than the 5.7° splitting angle of rutile. The absorption loss of the multilayer is reduced to 1 × 10^-3 dB/μm at λ = 1.3 μm. The magnitude of the residual stress is 9.45 × 10⁸ dyn/cm², which is about one-third of that prepared by the rf bias sputtering equipment which is used for another project of our group. The deposition rate of SiO₂, is increased to 135 nm/min, which is 27 times larger than that prepared by the sputtering equipment.     

Dual-band circularly polarized equilateral triangular-patch array antenna for mobile satellite communications

The Japan Aerospace Exploration Agency will launch the Engineering Test Satellite VIII (ETS-VIII) in 2006 to support the next generation of mobile satellite communications covering the area of Japan (beam coverage El=38/spl deg/ to 58/spl deg/). In this paper, a satellite-tracking left-handed circularly polarized triangular-patch array antenna is developed for ground applications. The targeted minimum gain of the antenna is set to 5 dBic at the central elevation angle (El=48/spl deg/), in the Tokyo area, for applications using data transfer of around a hundred kbps. The antenna is composed of three equilateral triangular patches for both reception and transmission units operating at 2.50 and 2.65 GHz frequency bands, respectively. The antenna was simulated by method of moments (MoM) analysis, and measurement of the fabricated antenna was performed to confirm the simulation results. The measurement results show that the frequency characteristics and the 5-dBic gain coverage in the conical-cut plane of the fabricated antenna satisfy the specifications for ETS-VIII. A prototype of the proposed antenna system is employed in outdoor experiments using a pseudosatellite and shows good performance from El=38/spl deg/ to 58/spl deg/.     

All-optical discrimination based on nonlinear transmittance of MQWsemiconductor optical gates

This paper proposes an all-optical regenerator utilizing a novel all-optical discriminator. The impacts of nonlinearity of optical gates on discrimination performance are estimated. The evaluation of discrimination performance shows that amplified spontaneous emission noise and wave form distortion in optical signals can be effectively suppressed. We experimentally demonstrate the suppression using a low-temperature-grown optical switch up to 10 Gb/s     

Submicrometer Comb-Drive Actuators Fabricated on Thin Single Crystalline Silicon Layer

Electrostatic comb-drive microactuators were fabricated by electron beam lithography on a 260-nm-thick silicon layer of a silicon-on-insulator wafer. The actuators consisted of comb electrodes, springs, and a frame. Two kinds of microactuators with doubly clamped and double-folded springs were designed and fabricated. The comb electrode was as small as 2.5 mum wide and 8 mum long and was composed of 250-nm-wide, 260-nm-thick, and 2-mum-long fingers. The air gap between the fingers was 350 nm. The spring was 250 nm wide, 260 nm thick, and 17.5 mum long, and the spring constant was 0.11 N/m. The force and displacement generated by the microactuator were 2.3 x 10^-7N and 1.0 mum, respectively. Applying an ac voltage, the oscillation amplitude became maximum at a frequency of 132 kHz. The mechanical and electrical characteristics of the fabricated actuators were investigated quantitatively.     

Fabrication method for IC-oriented Si single-electron transistors

A new fabrication method for Si single-electron transistors (SETs) is proposed. The method applies thermal oxidation to a Si wire with a fine trench across it on a silicon-on-insulator substrate. During the oxidation, the Si wire with the fine trench is converted, in a self-organized manner, into a twin SET structure with two single-electron islands, one along each edge of the trench, due to position-dependent oxidation-rate modulation caused by stress accumulation. Test devices demonstrated, at 40 K, that the twin SET structure can operate as two individual SET's. Since the present method produces two SET's at the same time in a tiny area, it is suitable for integrating logic circuits based on pass-transistor type logic and CMOS-type logic, which promises to lead to the fabrication of single-electron logic LSIs     

Comparative study of absorbing boundary conditions for thetime-domain beam propagation method

Various absorbing boundary conditions (ABCs) are compared in the analysis of the time-domain finite-difference beam propagation method. For a one-dimensional problem, the following ABCs are tested: Higdon's absorbing boundary, Ramahi's complementary operators method (COM), its concurrent version (C-COM) and Berenger's perfectly matched layer (PML). It is found that the second- and third-order C-COMs with three and four boundary cells are comparable to the PMLs with eight and 16 cells, respectively. The effectiveness of the C-COM is also discussed in a two-dimensional problem     

A multigigabit DRAM technology with 6F2 open-bitlinecell, distributed overdriven sensing, and stacked-flash fuse

A multigigabit DRAM technology was developed that features a low-noise 6F² open-bitline cell with fully utilized edge arrays, distributed overdriven sensing for operation below 1 V, and a highly reliable post-packaging repair scheme using a stacked-flash fuse. This technology, which can be used to fabricate a 0,13-μm 180-mm² 1-Gb DRAM assembled in a 400-mil package, was verified using a 57.6-mm², 200-MHz array-cycle, 256-Mb test chip with 0.109-μm² cells     

InP optical switch array module high frequency performance: measurements and analysis

An injection-mode InP optical switch array has been characterised at high frequency. A switched optical pulse settling anomaly, which limits the switching performance of the array, is associated with recombination and junction heating effects at the switch heterojunction interface. A simple model describing the effects is presented. Critical design parameters are also identified.<>     

Highly reliable copper dual-damascene interconnects with self-formed MnSi/sub x/O/sub y/ barrier Layer

Copper (Cu) dual-damascene interconnects with a self-formed MnSi/sub x/O/sub y/ barrier layer were successfully fabricated. Transmission electron microscopy shows that approximately 2-nm thick and continuous MnSi/sub x/O/sub y/ layer was formed at the interface of Cu and dielectric SiO/sub 2/, and that no barrier was formed at the via bottom because no oxygen was at the via bottom during annealing. No leakage-current increase was observed, and electron energy loss analysis shows that no Cu was in SiO/sub 2/, suggesting that MnSi/sub x/O/sub y/ layer has sufficient barrier properties for Cu, and that the concept of self-forming barrier process works in Cu dual-damascene interconnects. Via chain yield of more than 90% and 50% reduction in via resistance were obtained as compared with physical vapor deposited tantalum barrier, because there is no barrier at the via bottom. In addition, no failure in the stress-induced voiding measurement was found even after a 1600-h testing. No failure in electromigration (EM) testing was found, as the electron flow is from the lower level interconnects through via up to upper level interconnects even after 1000-h testing. At least, four times EM lifetime improvement was obtained in the case of electron flow from upper level interconnect through via down to lower level interconnects. Significant EM lifetime improvement is due to no flux divergence site at the via bottom, resulting from there being no bottom barrier at the via.