Silicon thermooptical micromodulator with 700-kHz -3-dB bandwidth

A silicon Fabry-Perot waveguide modulator, operating at the fiber optic communication wavelengths of 1.3 and 1.55 μm, has been entirely fabricated using microelectronic techniques. The planar optical cavity has been defined by plasma etching and has a length of 100 μm. The device, based on the thermooptic effect, is electrically driven and exhibits a maximum modulation depths of 60%. The measured -3 dB bandwidth is 700 kHz, which is by far the best result ever reported, to our knowledge, for thermooptic effect based modulators     

Silicon-on-silicon rib waveguides with a high-confiningion-implanted lower cladding

The realization of single-mode rib waveguides in standard epitaxial silicon layer on lightly doped silicon substrate, using ion implantation to form the lower cladding, is reported. The implanted buffer layer enhances' the vertical confinement and improves the propagation characteristics. Respect to similar standard all-silicon waveguides a propagation loss reduction of about 7 dB/cm, in the single-mode regime, has been measured. A numerical analysis has been performed to evaluate the theoretical attenuation and the transverse optical field profiles. As a result of the presence of the ion implanted buffer layer, an increase of the fundamental mode confinement factor from 0.3 to 0.85 has been calculated. This results in a great enhancement of the coupling efficiency with standard single-mode optical fibers. Moreover, the proposed technique is low cost, fully compatible with standard VLSI processes, and allows a great flexibility in the integration of guided-wave devices and electronic circuits. Finally, the very high thermal conductivity characterizing these waveguides makes them attractive host-structures for electrically and thermally controlled active optical devices     

High-performance noise-tolerant circuit techniques for CMOS dynamic logic

Dynamic CMOS gates are widely exploited in high-performance designs because of their speed. However, they suffer from high noise sensitivity. The main reason for this is the sub-threshold leakage current flowing through the evaluation network. This problem becomes more and more severe with continuous scaling of the technology. A new circuit technique for increasing the noise tolerance of dynamic CMOS gates is studied. A comparison with previously reported schemes is presented. Simulations proved that, when 90 nm CMOS technology is used to realise wide fan-in gates, the proposed design technique can achieve the highest level of noise robustness. A 16 bits OR gate designed as proposed here shows a maximum unity noise gain of 675 mV, a computational delay of 115 ps and an energy dissipation of 33 fJ. Moreover, at the parity of energy-delay product (EDP), the novel approach achieves a noise robustness 10% higher than the most efficient technique existing in the literature, whereas, at the parity of noise robustness, it exhibits an EDP 33% lower.     

Analysis of op-amp phase margin impact on SC ΣΔ modulator performance

The impact of operational amplifier (op-amp) phase margin on switched-capacitor (SC) sigma-delta modulator (ΣΔΜ) performance is investigated in this paper. An ad-hoc integrator settling model is developed and verified by circuit simulations performed in a commercial 0.35 μm CMOS technology. The model allows the effect of op-amp phase margin to be taken into account in ΣΔΜ behavioural analysis. Behavioural simulations of a typical single-bit second-order modulator are presented, as an example. As shown, the proposed analysis allows well-found specifications for the op-amp unity-gain frequency, slew rate and phase margin to be defined since the preliminary behavioural simulation phase.     

Efficient recursive multiply architecture for FPGAs

A new methodology for realising efficient multiply architectures for FPGAs is presented. The proposed strategy can be recursively applied to realise larger multipliers. Compared to proprietary macroblocks usually furnished within FPGA development tools, the new approach is more than 45% cheaper and more than 25% faster.     

Design approach for fast-settling two-stage amplifiers employing current-buffer Miller compensation

A new settling-time-oriented design strategy for two-stage operational amplifiers with current-buffer Miller compensation is presented. The proposed approach defines a systematic procedure to optimize the amplifier time response, allowing the required speed performances to be achieved without both power wasting and blind efforts for time-consuming trial-and-error design processes. To demonstrate the effectiveness of the methodology, a design example in a commercial 0.35 μm CMOS technology is presented. As shown by circuit and statistical simulations, the proposed strategy proves to be very useful to develop fast-settling operational amplifiers for typical discrete-time applications, such as switched-capacitor filters and ΣΔ analog-to-digital converters.