Implementation of scalable power and area efficient high-throughputViterbi decoders

Today's data reconstruction in digital communication systems requires designs of highest throughput rate at low power. The Viterbi algorithm is a key element in such digital signal processing applications. The nonlinear and recursive nature of the Viterbi decoder makes its high-speed implementation challenging. Several promising approaches to achieve either high throughput or low power have been proposed in the past. A combination of these is developed in this paper. Additional new concepts allow building a signal-flow graph suitable for the design of high-speed Viterbi decoders with low power. Using a flexible datapath generator facilitates the essential quantitative optimization from architectural down to physical level to fully exploit the low-power and high-speed potential of a given technology. With parameterizable design entry, this datapath generator establishes the basis of a scalable platform-based design library. Altogether, this allows coverage of the range of today's industrial interest in high throughput rates, from 150 Msymbols/s up to 1.2 Gsymbols/s using conventional CMOS logic. The features of two exemplary Viterbi decoder implementations prove the benefit of this physically oriented design methodology in terms of speed and low power, when compared to other leading edge implementations     

Design optimization of low-power high-performance DSP building blocks

In recent years, power dissipation along with silicon area has become the key figure in chip design. The increasing demands on system performance require high-performance digital signal processing (DSP) systems to include dedicated number-crunching units as individually optimized building blocks. The various design methodologies in use stress one of the following figures: power dissipation, throughput, or silicon area. This paper presents a design methodology reducing any combination of cost drivers subject to a specified throughput. As a basic principle, the underlying optimization regards the existing interactions within the design space of a building block. Crucial in such optimization is the proper dimensioning of device sizes in contrast to the common use of minimal dimensions in low-power implementations. Taking the design space of an FIR filter as an example, the different steps of the design process are highlighted resulting in a low-power high-throughput filter implementation. It is part of an industrial read-write channel chip for hard disks with a worst case throughput of 1.6 GSamples/s at 23 mW in a 0.13-/spl mu/m CMOS technology. This filter requires less silicon area than other state-of-the-art filter implementations, and it disrupts the average trend of power dissipation by a factor of 6.     

Melt Instability Identification Using Unsupervised Machine Learning Algorithms

In industrial extrusion processes, increasing shear rates can lead to higher production rates. However, at high shear rates, extruded polymers and polymer compounds often exhibit melt instabilities ranging from stick-slip to sharkskin to gross melt fracture. These instabilities result in challenges to meet the specifications on the extrudate shape. Starting with an existing published data set on melt instabilities in polymer extrusion, we assess the suitability of clustering, unsupervised machine learning algorithms combined with feature selection, to extract and identify hidden and important features from this data set, and their possible relationship with melt instabilities. The data set consists of both intrinsic features of the polymer as well as extrinsic features controlled and measured during an extrusion experiment. Using a range of commonly available clustering algorithms, it is demonstrated that the features related to only the intrinsic properties of the data set can be reliably divided into two clusters, and that in turn, these two clusters may be associated with either the stick-slip or sharkskin instability. Furthermore, using a feature ranking on both the intrinsic and extrinsic features of the data set, it is shown that the intrinsic properties of molecular weight and polydispersity are the strongest indicators of clustering.     

结合时空掩码和空间二维位置编码的手势识别

目的 在动态手势序列特征提取时,忽略了不同动态手势手指间的相关性,是造成手势识别率不高的重要原因。针对此问题,提出了时空位置编码和掩码的方法进行手势识别,是首次对手部关节点进行空间二维位置编码。方法 首先,根据手部关节序列构造时空图,利用关节点平面坐标生成空间二维编码,并与时间轴的一维编码器融合,生成关节点的时空位置编码,可以有效处理空间上的异常姿态同时避免时间上的乱序问题;然后,将时空图按照人体手部生物结构进行分块,通过空间自注意力和空间掩码,获取手指与手指之间的潜在信息。采用时间维度扩张的策略,通过时间自注意力和时间掩码,捕获长时间手指序列动态演变信息。结果 在DHG-14/28（dynamichand gesture 14/28）数据集上,该算法比HPEV（hand posture evolution volume）算法平均识别率高出4.47%,比MS-ISTGCN（multi-stream improved spatio-temporal graph convolutional network）算法平均识别率高出2.71%;在SHREC’17 track数据集上,该算法比HPEV算法平均识别率高出0.47%,利用消融实验证明了本文策略的合理性。结论 通过大量实验评估,验证了基于分块和时空位置编码构造出来的模型很好地解决了上述问题,提高了手势识别率。