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21.
Multifunctional 3D Patternable Drug‐Embedded Nanocarrier‐Based Interfaces to Enhance Signal Recording and Reduce Neuron Degeneration in Neural Implantation 下载免费PDF全文
22.
无刷同步电机的励磁系统对励磁电流的测量是制约该励磁方式发展的一大障碍。设计了一个射频系统可以用来解决同步电机的励磁电流的测量问题。该系统可以方便地检测到同步电机励磁机的整流二极管的工作状态并且可以动态地显示励磁电流,极大地方便了运行人员做出判断,而且结构简单、方便实用。 相似文献
23.
1概述
近十多年来,随着电力电子技术、微电子技术及现代控制理论的发展,变频调速技术已经广泛地用于交流电动机的速度控制,其最主要的特点是具有高效率的驱动性能及良好的控制特性.它是一种高新技术电力节能装置,它通过改变(降低)电源工作频率,来降低动力设备(电机)的转速,减少设备的输出功率,达到输出功率与工作负荷的最佳匹配,实现节能目的,有效地提高了经济效益和产品质量.几乎可以说,有电动机的地方就有变频器,在一切需要进行速度控制的场合,变频器以其操作方便、体积小、控制性能高而获得广泛应用. 相似文献
24.
High-performance and power-efficient CMOS comparators 总被引:1,自引:0,他引:1
Chung-Hsun Huang Jinn-Shyan Wang 《Solid-State Circuits, IEEE Journal of》2003,38(2):254-262
Several design techniques for high-performance and power-efficient CMOS comparators are proposed. First, the comparator is based on the priority-encoding (PE) algorithm, and the dynamic circuit technique developed specifically for the priority encoder can be applied. Second, the PE function and the subsequent logic functions are merged and efficiently realized in the multiple output domino logic (MODL) to result in a shortened logic depth. The circuit in MODL CMOS is also compact and power efficient because few transistors are needed. Third, the multilevel look-ahead technique is used to shorten the path of priority-token propagation. Finally, the circuit is realized with a latch-based two-stage pipelined structure, and the comparison function is partitioned into two parts, with each part executed in each half of the clock cycle in a delay-balanced manner. Post-layout simulation results show that a 64-b comparator designed with the proposed techniques in a 3-V 0.6-/spl mu/m CMOS technology is 16% faster, 50% smaller, and 79% more power efficient as compared with the all-n-transistor comparator, which is the fastest among the conventional comparators. Measurement results of the test chip conform with simulation results and prove the feasibility of the proposed techniques. 相似文献
25.
以Si-MCM-41、Al-MCM-41(1) (n(Si)/n(Al)=15)、Al-MCM-41(2) (n(Si)/n(Al)=10)以及用NH4NO3或HAc的醇溶液分别与Si-MCM-41离子交换所得的H-MCM-41(N)和H-MCM-41(H)为载体制备了系列Ru/MCM-41催化剂。采用N2吸附、XRD和H2-TPR表征了负载Ru前后催化剂的结构及Ru在各种载体表面上的分散状态。以0.5%(质量分数)苯的环己烷溶液为模型化合物,在298K、3.0MPa反应条件下,考察了上述催化剂的苯液相加氢反应性能,并与Ru/HY、Ru/H61538;和Pt/MCM-41催化剂进行了比较。结果表明,载体MCM-41的n(Si)/n(Al)和表面化学组成等性质对Ru在其表面上的分散状态、还原性及催化性能均有影响。对苯的转化率与反应时间的关系曲线进行拟合,发现其遵循一级动力学方程,加氢反应速率常数按照Ru/Al-MCM-41(2)相似文献
26.
Rogin J. Kouchev I. Brenna G. Tschopp D. Qiuting Huang 《Solid-State Circuits, IEEE Journal of》2003,38(12):2239-2248
A 2-GHz direct-conversion receiver for wide-band code division multiple access (WCDMA) is presented. It includes two low-noise amplifiers (LNAs), an I/Q demodulator, and two sixth-order baseband channel select filters with programmable gain. Quadrature local oscillator (LO) signals are generated on chip in a frequency divider flip-flop. An external interstage filter between the LNAs rejects transmitter leakage to relax demodulator linearity requirements. A low-voltage demodulator topology improves linearity as well as demodulator output pole accuracy. The active-RC baseband filter uses a programmable servo loop for offset compensation and provides an adjacent channel rejection of 39 dB. Programmable gain over 71-dB range in 1-dB steps is merged with the filter to maximize dynamic range. An automatic on-chip frequency calibration scheme provides better than 1.5% corner frequency accuracy. The receiver is integrated in a 0.13-/spl mu/m CMOS process with metal-insulator-metal (MIM) capacitors. Measured receiver performance includes a 6.5-dB noise figure, IIP2 of +27 dBm, and IIP3 of -8.6 dBm. Power consumption is 45 mW. 相似文献
27.
Xue‐Yong Liu Xiao‐Bin Ding Zhao‐Hui Zheng Yu‐Xing Peng Albert S
C Chan C
W Yip Xin‐Ping Long 《Polymer International》2003,52(2):235-240
Amphiphilic magnetic microspheres ranging in diameter from 5 to 100 µm were prepared by dispersion copolymerization of styrene and poly(ethylene oxide) vinylbenzyl (PEO‐VB) macromonomer (MPEO) in the presence of Fe3O4 magnetic fluid. The effects of various polymerization parameters on the average particle size were systematically investigated. The average particle size was found to increase with increasing styrene concentration and initiator concentration. It also increased with decreasing stabilizer concentration and molecular weight of MPEO. The content of the hydroxyl groups localized in the microspheres ranged from 0.01 to 0.2 mmol g?1. © 2003 Society of Chemical Industry 相似文献
28.
29.
Analysis and architecture design of variable block-size motion estimation for H.264/AVC 总被引:1,自引:0,他引:1
Ching-Yeh Chen Shao-Yi Chien Yu-Wen Huang Tung-Chien Chen Tu-Chih Wang Liang-Gee Chen 《IEEE transactions on circuits and systems. I, Regular papers》2006,53(3):578-593
Variable block-size motion estimation (VBSME) has become an important video coding technique, but it increases the difficulty of hardware design. In this paper, we use inter-/intra-level classification and various data flows to analyze the impact of supporting VBSME in different hardware architectures. Furthermore, we propose two hardware architectures that can support traditional fixed block-size motion estimation as well as VBSME with less chip area overhead compared to previous approaches. By broadcasting reference pixel rows and propagating partial sums of absolute differences (SADs), the first design has the fewer reference pixel registers and a shorter critical path. The second design utilizes a two-dimensional distortion array and one adder tree with the reference buffer that can maximize the data reuse between successive searching candidates. The first design is suitable for low resolution or a small search range, and the second design has advantages of supporting a high degree of parallelism and VBSME. Finally, we propose an eight-parallel SAD tree with a shared reference buffer for H.264/AVC integer motion estimation (IME). Its processing ability is eight times of the single SAD tree, but the reference buffer size is only doubled. Moreover, the most critical issue of H.264 IME, which is huge memory bandwidth, is overcome. We are able to save 99.9% off-chip memory bandwidth and 99.22% on-chip memory bandwidth. We demonstrate a 720-p, 30-fps solution at 108 MHz with 330.2k gate count and 208k bits on-chip memory. 相似文献
30.
以2个小水电站径流计算为实例,分析移用降雨径流关系和参证站选择的教训,对改进小水电站径流计算方法提出了建议。表4个。 相似文献