At least N+1 finite transmission zeros using frequency-variant negative source-load coupling

A second-order cross-coupled combline filter which has three finite transmission zeros is presented. The problem of the frequency-invariant coupling in a real circuit is introduced. To make extra transmission zeros, a top metalized dielectric block is used.     

High-performance 94-GHz single balanced mixer using 70-nm MHEMTs and surface micromachined technology

We reported 94-GHz, low conversion loss, and high isolation single balanced active gate mixer based on 70-nm gate length InGaAs/InAlAs metamorphic high-electron mobility transistors (MHEMTs). This mixer showed that the conversion loss and isolation characteristics were 2.5/spl sim/3.5 dB and under -29 dB in the range of 92.95/spl sim/94.5 GHz, respectively. The low conversion loss of the mixer is mainly attributed to the high-performance of the MHEMTs exhibiting a maximum drain current density of 607 mA/mm, an extrinsic transconductance of 1015 mS/mm, a current gain cutoff frequency (f/sub t/) of 330 GHz, and a maximum oscillation frequency (f/sub max/) of 425 GHz. High isolation characteristics are due to hybrid ring coupler which adopted dielectric-supported air-gapped microstrip line structure using surface micromachined technology. To our knowledge, these results are the best performance demonstrated from 94 GHz single balanced mixer utilizing GaAs-based HEMTs in terms of conversion loss as well as isolation characteristics.     

Curved Projection Integral Imaging Using an Additional Large‐Aperture Convex Lens for Viewing Angle Improvement

In this paper, we propose a curved projection integral imaging system to improve the horizontal and vertical viewing angles. The proposed system can be easily implemented by additional use of a large‐aperture convex lens in conventional projection integral imaging. To obtain the simultaneous display of 3D images through real and virtual image fields, we propose a computer‐generated pickup method based on ray optics and elemental images, which are synthesized for the proposed system. To show the feasibility of the proposed system, preliminary experiments are carried out. Experimental results indicate that our system improves the viewing angle and displays 3D images simultaneously in real and virtual image fields.     

Monolithic arrays of surface emitting laser NOR logic devices

Monolithic, cascadable, laser-logic-device arrays have been realized and characterized. The monolithic surface-emitting laser logic (SELL) device consists of an AlGaAs superlattice lasing around 780 nm connected to a heterojunction phototransistor (HPT) in parallel and a resistor in series. Arrays up to 8×8 have been fabricated, and 2×2 arrays show uniform characteristics. The optical logic output is switched off with 40 μW incident optical input     

A simple yet effective technique for partitioning

Partitioning is an important step in the top-down design of large complicated integrated circuits. In this paper, a simple yet effective partitioning technique is described. It is based on the clustering of “closely” connected cells and the gradual enforcement of size-constraints. At the beginning, clusters are formed in the bottom-up fashion to reduce the problem size. Then the clusters are partitioned using several different parameters to find a good starting point. The best result achieved during the cluster partitioning is used as the initial solution for the lower level partitioning. The gradual constraint enforcement technique is used to cope with the local minimum problems. It allows cells or clusters to move with more freedom among the subsets during earlier iterations and thus may effectively find a near optimum solution. Several experimental results show that the new partitioning technique produces favorable results. In particular, the method outperforms the F&M method by more than 60% in the number of crossing nets on average     

InSb,GaSb, and GaInSb grown using trisdimethylaminoantimony

GalnSb alloys as well as the constituent binaries InSb and GaSb have been grown by organometallic vapor phase epitaxy using the new antimony precursor trisdimethylaminoantimony (TDMASb) combined with conventional group III precursors trimethylindium (TMIn) and trimethylgallium (TMGa). InSb layers were grown at temperatures between 275 and 425°C. The low values of V/III ratio required to obtain good morphologies at the lowest temperatures indicate that the pyrolysis temperature is low for TDMASb. In fact, at the lowest temperatures, the InSb growth efficiency is higher than for other antimony precursors, indicating the TDMASb pyrolysis products assist with TMIn pyrolysis. A similar, but less pronounced trend is observed for GaSb growth at temperatures of less than 500°C. No excess carbon contamination is observed for either the InSb or GaSb layers. Ga_1-xIn_xSb layers with excellent morphologies with values of x between 0 and 0.5 were grown on GaSb substrates without the use of graded layers. The growth temperature was 525°C and the values of V/III ratio, optimized for each value of x, ranged between 1.25 and 1.38. Strong photoluminescence (PL) was observed for values of x of less than 0.3, with values of halfwidth ranging from 13 to 16 meV, somewhat smaller than previous reports for layers grown using conventional precursors without the use of graded layers at the interface. The PL intensity was observed to decrease significantly for higher values of x. The PL peak energies were found to track the band gap energy; thus, the luminescence is due to band edge processes. The layers were all p-type with carrier concentrations of approximately 10¹⁷ cm³. Transmission electron diffraction studies indicate that the Ga_0.5In_0.5 Sb layers are ordered. Two variants of the Cu-Pt structure are observed with nearly the same diffracted intensities. This is the first report of ordering in GalnSb alloys.     

Room temperature characterization of Hg1-xCdxTe P-on-n heterostructure photodiodes

Measurements of 77K R_oA and 300K reverse bias dynamic impedance (R_dA) products at one volt reverse bias has been carried out to assess the degree of correlation of this figure of merit. Planar P-on-n heterostructures were grown on near lattice-matched CdZnTe substrates with Hg_1-xCd_xTe (0.20< x <0.30) by molecular beam epitaxy. These devices were passivated with CdTe and doped with indium and arsenic as n- and p-type dopants, respectively. Current-voltage characteristic of these devices exhibit thermally generated dark currents at small and modest reverse bias. We have observed that R_oA values of these long wavelength infrared P-on-n heterostructure photodiodes at 77K correlate with room temperature R_dA values. Diode arrays with high room temperature R_dA values at one volt reverse bias also have high R_oA values at 77K. Similarly, low R_dA values at room temperature indicate poor performance at 77K where deviation from diffusion current occurs at reverse bias of 0.2 to 1 volt at room temperature. The results presented here, for a small samples of devices, demonstrate that room temperature measurements of current-voltage characteristics to evaluate Hg_1-xCd_xTe (0.22< x <0.28) diode performance and array uniformity at lower temperatures can be used. This provides an acceptable criteria for further study at lower temperatures.     

Simple ASK transmitter using a 790 nm self-pulsating laser diodefor local area networks

A simple amplitude shift keying (ASK) optical link is demonstrated by using a low-cost self-pulsating laser diode and an envelope detector for a low-cost broadband local area network. A link sensitivity of -22 dBm was achieved at 200 Mbit/s. Because the self-pulsation frequency can be tuned by the bias current, frequency division multiplexing can be simply implemented for multiuser applications     

Simulating process-induced gate oxide damage in circuits

Advanced processing techniques such as plasma etching and ion implantation can damage the gate oxides of MOS devices and thus pose a problem to circuit reliability. In this paper, we present a simulator which predicts oxide failure rates during and after processing and pinpoints strong charging current locations in the layout where changes can be made to improve circuit hot-carrier reliability. We present the models and experimental results used to develop the simulator and demonstrate the usefulness of this simulator