Surface copper enrichment by reduction of copper chromite catalyst employed for carbon monoxide oxidation

The effect of prereduction on CO oxidation activity of unsupported copper-chromite oxide catalysts was examined. Results were found to be in good agreement with two mechanisms for a surface copper enrichment due to CO prereduction which produced an activity increase in the copper-chromite catalyst.     

Ultrasonic Dispersion of Ceramic Powders

Ultrasonication is very effective in dispersing alumina and barium titanate slurries. When optimum conditions are used, very short durations (2 to 3 min) are enough to achieve well-dispersed, stable suspensions.     

An energy efficient middleware for an ad-hoc AAL wireless sensor network

DIA (Dispositivo Inteligente de Alarma, in Spanish) is an AAL (Ambient Assisted Living) system that allows to infer a potential dangerous action of an elderly person living alone at home. This inference is obtained by a specific sensorisation with sensor nodes (portables and fixes) and a reasoning layer embedded in a PC that learns of the users behaviour patterns and advices when actual one differs significantly of the normal patterns. In AAL systems, energy is a limited resource therefore sensor devices need to be properly managed to conserve energy. In this paper, we introduce the design and implementation of innovative and specific mechanisms at the sensory layer middleware which is capable of, first to discriminate spurious motion detections assuming that these signals do not resemble the patterns of real motion detections and, second to reduce the dynamics of messages by a sensor signal processing in order to compress the whole information in one single event. The middleware achieves power saving by modifying the raw information from sensors and adapting it to the predefined semantic of the reasoning layer. It manages the important task of data processing from sensors (raw information), and transfers the pre-processed information into the top layer of reasoning in a more energy efficient way. We also address the trade-off between reducing power consumption and reducing delay for incoming data. We present results from experiments using our implementation of these mechanisms at the middleware that comprises from node firmware to the PC driver. The number of messages of the proposed method with respect to the raw data is reduced by approximately 98.5%. The resources used in the PIR signal processing is reduced by approximately 85%. The resulting delay introduced is small (10–19 s) but system dynamics is slow enough to avoid contextualisation errors or reduction of system performance. We consider these results as very satisfactory.     

Dynamic modeling of tunable analog integrated filters for a stability study of on-chip automatic tuning loops

Continuous-time filters with automatic tuning loops are nonlinear feedback systems that are potentially unstable. To ensure stability, particularly if the design of the loop controllers is to be improved, the appropriate linear dynamic modeling of the tunable filter, including control inputs, should be attained. This work aims to present a general dynamic modeling of continuous-time analog filters with automatic tuning capability. The general analysis leads to an equivalent small-signal linearized incremental model, from which transfer functions between output variables and control voltages are obtained. Subsequent to the analysis, it is possible to design compensated loops with enhanced stability and dynamic performance. By way of example, the modeling of a particular band-pass CMOS continuous-time analog filter is presented in this paper. Two transfer functions are derived: the transfer function between the output phase shift and the central frequency control voltage, and that between the output amplitude and the quality factor control voltage. These functions are required to properly tune the central frequency and quality factor parameters. This modeling makes it possible to propose an adaptive controller with improved stability and a possible implementation for such a controller. Finally, experimental results are shown for a CMOS 0.8 μm technology.     

An efficiently implementable maximum likelihood decoding algorithm for tailbiting codes

Convolutional tailbiting codes are widely used in mobile systems to perform error-correcting strategies of data and control information. Unlike zero tail codes, tailbiting codes do not reset the encoder memory at the end of each data block, improving the code efficiency for short block lengths. The objective of this work is to propose a low-complexity maximum likelihood decoding algorithm for convolutional tailbiting codes based on the Viterbi algorithm. The performance of the proposed solution is compared to that of another maximum likelihood decoding strategy which is based on the A* algorithm. The computational load and the memory requirements of both algorithms are also analysed in order to perform a fair comparison between them. Numerical results considering realistic transmission conditions show the lower memory requirements of the proposed solution, which makes its implementation more suitable for devices with limited resources.     

A survey on nonlinear analog-to-digital converters

This paper presents a survey on Nonlinear Analog-to-Digital converters (ADC). This class of converters is extremely relevant in applications where there is a need for non-uniform quantization characteristic, for example, some specific applications in the areas of light detection, hearing aid, nuclear physics, image acquisition, communication systems, etc. This survey outlines the state-of-the-art Nonlinear ADC topologies, such as, floating point, logarithmic, piecewise linear and oversampled nonlinear converters, and discusses their performance and advantages in terms of their applications.     

A 0.8 μm CMOS testable switched-capacitor filter for video frequency applications

This paper presents the design of a fifth-order low-pass elliptic filter that employs a parallel connection of two all-pass sections to satisfy specifications commonly used in video frequency applications. Operating with a sampling frequency of 16 MHz, the IC prototype was implemented in a standard double-poly CMOS 0.8 μm process. The experimental verification showed a passband frequency deviation smaller than 0.08 dB up to the passband edge frequency of 3.4 MHz, and an output noise power of 0.97 ${\mu {\rm V}_{\rm RMS}}/{\sqrt {Hz}}This paper presents the design of a fifth-order low-pass elliptic filter that employs a parallel connection of two all-pass sections to satisfy specifications commonly used in video frequency applications. Operating with a sampling frequency of 16 MHz, the IC prototype was implemented in a standard double-poly CMOS 0.8 μm process. The experimental verification showed a passband frequency deviation smaller than 0.08 dB up to the passband edge frequency of 3.4 MHz, and an output noise power of 0.97 , resulting in a dynamic range of 49.1 dB. The filter structure enables multiple fault detection and suits modern automated testing configurations to allow accurate estimation of the actually implemented transfer function parameters, an issue of increasing importance in VLSI circuit design. The relative area required for testing the fifth-order filter is only 8% of the total filter area, and decreases as the filter order increases. Jorge Morales Ca?ive was born in Cienfuegos, Cuba, in 1963. He received the B.Sc. and M.Sc. degrees from the Technical University of San Petersburg, Russia, in 1986 and 1988, respectively, and the D.Sc. degree from the Federal University of Rio de Janeiro, Brazil, in 1991, all in electrical engineering. From 1988 to 1994, he worked at CEADEN, in Havana, Cuba, on the development of nuclear equipments. From 1994 to 1997, he worked at INOR, in Havana, Cuba, on the research and development of acquisition systems and image processing for nuclear medicine. His research interests are in the areas of analog and digital signal processing. Antonio Petraglia (S’89-M’91-SM’99) received the Engineer and M.Sc. degrees from the Federal University of Rio de Janeiro (UFRJ), Brazil, in 1977 and 1982, respectively, and the Ph.D. degree from the University of California, Santa Barbara (UCSB), in 1991, all in electrical engineering. In 1979, he joined the Faculty of UFRJ as an Associate Professor of electrical engineering, where he served as a Co-Chair in the Department of Electronic Engineering from 1982 to 1984. During the second semester of 1991, he was a post-Doctoral researcher with the Department of Electrical and Computer Engineering at UCSB. Since 1992 he has been on the faculty of the Program for Post-Graduate Engineering at UFRJ, where in 1997 he established the Laboratory for the Processing of Analog and Digital Signals. From March 2001 through March 2002 he was a Visiting Scholar with the Electrical Engineering Department at the University of California, Los Angeles. He has been involved in teaching and research activities in the areas of analog and digital signal processing, and in mixed analog-digital integrated circuit design. He is a distinguished member of the Brazilian Millenium Group in Nanoelectronics and Microelectronics in 2006-2008. Dr. Petraglia served as an Associate Editor for the IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing in 2002–2003 Mariane Rembold Petraglia (M’97) received the B.Sc. degree in electronic engineering from the Federal University of Rio de Janeiro, Brazil, in 1985, and the M.Sc. and Ph.D. degrees in electrical engineering from the University of California, Santa Barbara, in 1988 and 1991, respectively. From 1992 to 1993, she was with the Department of Electrical Engineering, Catholic University of Rio de Janeiro, Brazil. Since 1993, she has been with the Department of Electronic Engineering and with the Program of Electrical Engineering, COPPE, at the Federal University of Rio de Janeiro, where she is presently an Associate Professor. From March 2001 to February 2002, she was a Visiting Researcher with the Adaptive Systems Laboratory, at the University of California, Los Angeles. Her research interests are in adaptive signal processing, multirate systems, and image processing. Dr. Petraglia is a member of Tau Beta Pi, and a distinguished member of the Brazilian Millenium Group in Nanoelectronics and Microelectronics in 2006–2008. She is serving as an Associate Editor for the IEEE Transactions on Signal Processing since Nov. 2004.     

Understanding Soliton Wave Propagation in Nonlinear Transmission Lines for Millimeter Wave Multiplication

In this paper, soliton propagation in nonlinear transmission lines (NLTLs) periodically loaded with symmetric voltage dependent capacitances is studied. From the lumped element equivalent circuit of the line we have analyzed the influence of nonlinear shunt reactances on soliton propagation characteristics. It is shown that by increasing the non linearity of the C–V characteristic, a faster separation of input signal into solitons is achieved. The fact that frequency multiplication in NLTLs is governed by soliton formation makes the results of this work relevant to understand the influence of nonlinear loading devices on multiplier performance. Since a heterostructure barrier varactor (HBV)-like voltage dependent capacitance has been considered for the nonlinear devices, this study can be of interest for the design of millimeter wave frequency multipliers loaded with HBVs.     

High-Speed High-Precision CMOS Current Conveyor

In this paper a new class-AB CMOS second generation current conveyor (CCII) based on a novel high-performance voltage follower topology is proposed. Post-layout simulation results from a 0.8 m design supplied at 3.3 V show very low resistance at node X (<50 ), high frequency operation (100 MHz), high precision in the voltage and current transference and reduced offset. As application examples, a V-I converter and a current feedback operational amplifier (CFOA) have been implemented. The latter presents slew-rate levels higher than ±100 V/s.