Analysis of Input Filter Interactions in Switching Power Converters

This paper presents the theoretical and practical details involved with the small-signal analysis of switching power converters under a strong influence of input filter interaction. A boost dc-to-dc converter controlled by voltage-mode control and the same boost converter controlled by current-mode control are used as illustrative examples. The theoretical predictions of this paper are supported by experimental results and computer simulations     

Toward Advanced Mobile Cloud Computing for the Internet of Things: Current Issues and Future Direction

Cloud computing is the coming new era of information processing and has proved its benefits in high scalability and functional diversity. However, almost all cloud-computing architectures including SaaS, PaaS, and IaaS are vulnerable to serious security issues. Similarly, Mobile Cloud Computing (MCC) is vital to overcoming mobile limited storage and computing capabilities. MCC authentication and authorization issues must be provided on two levels: login password control and the environment from where the cloud is accessed. MCC has overcome the barrier of limited storage by providing remote storage but requires a strict security system that is responsible for retrievability, integrity, and seamless storage access. Elasticity and connectivity are also of major concern in MCC because delays and jitters cause degradation in the user experience. Cloud-computing architecture creates more challenges in maintaining security because of the liberty of users to choose any MCC architecture. Thus in this paper we discuss current cloud computing issues and future directions.     

Discrete-time analysis of a CPCH access scheme in W-CDMA

Common packet channel (CPCH) access is an efficient approach to support packet data transmissions in a wideband code division multiple access (W-CDMA) system. Rather than using a continuous-time analysis approach, this paper presents a discrete-time analysis of the CPCH access scheme to fully characterize the complete CPCH operation process. Previous studies using the continuous-time analysis only models a portion of the CPCH process. We assume that a packet arrival process is Poisson distributed and the service time of each packet is geometrically distributed. The study focuses on examining the number of packet arrivals in each CPCH access slot. Performance is evaluated in terms of normalized throughput and it is observed that CPCH performs better when packet mean service time is larger. The performance results are also compared with previous studies using continuous-time analyses     

Effect of Gold on the Corrosion Behavior of an Electroless Nickel/Immersion Gold Surface Finish

The performance of surface finishes as a function of the pH of the utilized plating solution was evaluated by electrochemical impedance spectroscopy (EIS) and potentiodynamic polarization tests in 3.5 wt.% NaCl solution. In addition, the surface finishes were examined by x-ray diffraction (XRD), and the contact angle of the liquid/solid interface was recorded. NiP films on copper substrates with gold coatings exhibited their highest coating performance at pH 5. This was attributed to the films having the highest protective efficiency and charge transfer resistance, lowest porosity value, and highest contact angle among those examined as a result of the strongly preferred Au(111) orientation and the improved surface wettability.     

Millimeter‐Wave High‐Linear CMOS Low‐Noise Amplifier Using Multiple‐Gate Transistors

A millimeter‐wave (mm‐wave) high‐linear low‐noise amplifier (LNA) is presented using a 0.18 µm standard CMOS process. To improve the linearity of mm‐wave LNAs, we adopted the multiple‐gate transistor (MGTR) topology used in the low frequency range. By using an MGTR having a different gate‐source bias at the last stage of LNAs, third‐order input intercept point (IIP3) and 1‐dB gain compression point (P_1dB) increase by 4.85 dBm and 4 dBm, respectively, without noise figure (NF) degradation. At 33 GHz, the proposed LNAs represent 9.5 dB gain, 7.13 dB NF, and 6.25 dBm IIP3.     

Highly Power‐Efficient Rack‐Level DC Power Architecture Combined with Node‐Level DC UPS

This letter presents a highly efficient rack‐level DC power architecture combined with a node‐level DC uninterruptible power supply (UPS). The proposed system can provide almost the equivalent power efficiency of a high‐voltage DC data center without any change in the existing power infrastructure. The node‐level DC UPS combined with a power distribution board provides high power efficiency as well as lower UPS installation costs. Implemented on a rack, the entire power system can be monitored through a network.     

1.5 V Sub‐mW CMOS Interface Circuit for Capacitive Sensor Applications in Ubiquitous Sensor Networks

In this paper, a low‐power CMOS interface circuit is designed and demonstrated for capacitive sensor applications, which is implemented using a standard 0.35‐μm CMOS logic technology. To achieve low‐power performance, the low‐voltage capacitance‐to‐pulse‐width converter based on a self‐reset operation at a supply voltage of 1.5 V is designed and incorporated into a new interface circuit. Moreover, the external pulse signal for the reset operation is made unnecessary by the employment of the self‐reset operation. At a low supply voltage of 1.5 V, the new circuit requires a total power consumption of 0.47 mW with ultra‐low power dissipation of 157 μW of the interface‐circuit core. These results demonstrate that the new interface circuit with self‐reset operation successfully reduces power consumption. In addition, a prototype wireless sensor‐module with the proposed circuit is successfully implemented for practical applications. Consequently, the new CMOS interface circuit can be used for the sensor applications in ubiquitous sensor networks, where low‐power performance is essential.