Two-dimensional GaAs photonic switch array with direct gain andhigh contrast

The fabrication and design of a 4×4 surface-normal reflection photonic switch array, with an operating principle based on the change of the gain coefficient in GaAs, is described. A 3-μm-thick GaAs active layer and carrier confinement layers are sandwiched between a semiconductor multilayer reflector and an antireflection window. The beryllium ion implantation technique is used to make a narrow current path to reduce the operation current. Each photonic switch independently realizes direct amplification and absorption of the optical signal. It features an optical gain of 4 dB and a contrast of 9.6 dB, for an applied voltage of 2.2 V. The array has a simple planar structure     

Historical review of OCR research and development

Research and development of OCR systems are considered from a historical point of view. The historical development of commercial systems is included. Both template matching and structure analysis approaches to R&D are considered. It is noted that the two approaches are coming closer and tending to merge. Commercial products are divided into three generations, for each of which some representative OCR systems are chosen and described in some detail. Some comments are made on recent techniques applied to OCR, such as expert systems and neural networks, and some open problems are indicated. The authors' views and hopes regarding future trends are presented     

High-Speed TDM–WDM Techniques for Long-Haul Submarine Optical Amplifier Systems

Optical amplifier techniques have led to the installation of large-capacity submarine systems and further capacity increases seem likely. This paper reviews the FSA submarine system, which flexibly operates at both 2.5 and 10 Gb/s and offers maximum transmission capacity of 60 Gb/s for commercial use. The system configuration as well as its characteristics and upgradability will be introduced, including measurement results on time-division-multiplexing/wavelength-division-multiplexing (TDM–WDM) transmission at bit rates of 10 and 20 Gb/s using non-return-to-zero or soliton pulses. To further increase transmission capacity, TDM–WDM techniques that permit more than 10 Gb/s signal transmission in each data channel should be developed. Thus, pulse formats, which include non-return-to-zero, return-to-zero, or soliton pulses, and dispersion allocation in transmission fibers are significant issues. We introduce and discuss our recent results from high-speed (10 to 40 Gb/s) TDM–WDM signal transmission experiments with regard to the above aspects.     

Fabrication and current-drive of SiGe/Si 'Micro-origami' epitaxial MEMS device on SOI substrate

A micromirror structure with SiGe/Si heteroepitaxial layer on a silicon-on-insulator (SOI) substrate using a 'Micro-origami' technique has been successfully fabricated. The micromirror is supported by two curved hinge structures. The device is driven by application of a current, and net angular displacements larger than 10/spl deg/ (static) and 30/spl deg/ (in resonance) were obtained. These values are comparable with or even larger than the reported values for other MEMS optical switches or beam scanning devices. The experimental results suggest that the movement is evoked by a thermal effect. The Micro-origami device has advantages of low operation voltage smaller than 2 V, and structural compatibility with the Si or SiGe LSIs.     

Gain-flattened tellurite-based EDFA with a flat amplificationbandwidth of 76 nm

We describe a tellurite-based Er³⁺-doped fiber amplifier (EDFA) with a flat amplification bandwidth of 76 nm and a noise figure of less than 7 dB. Furthermore, a parallel-type amplifier composed of this EDFA and a 1.45-μm-band Tm³⁺-doped fluoride fiber amplifier achieved a flat amplification bandwidth of 113 nm     

Thickness scaling limitation factors of ONO interpoly dielectricfor nonvolatile memory devices

This paper describes the scaling limitation factors of ONO interpoly dielectric thickness, mainly considering the charge retention capability and threshold voltage stability for nonvolatile memory cell transistors with a stacked-gate structure, based on experimental results. For good intrinsic charge retention capability, either the top- or bottom-oxide thickness should be greater than around 6 nm. On the other hand, a thicker top oxide structure is preferable to minimize degradation due to defects. It has been confirmed that a 3.2 nm bottom-oxide shows detectable threshold voltage instability, but 4 nm does not. Effective oxide thickness scaling down to around 13 nm should be possible for flash memory devices with a quarter-micron design rule     

A CMOS multichannel 10-Gb/s transceiver

We describe a CMOS multichannel transceiver that transmits and receives 10 Gb/s per channel over balanced copper media. The transceiver consists of two identical 10-Gb/s modules. Each module operates off a single 1.2-V supply and has a single 5-GHz phase-locked loop to supply a reference clock to two transmitter (Tx) channels and two receiver (Rx) channels. To track the input-signal phase, the Rx channel has a clock recovery unit (CRU), which uses a phase-interpolator-based timing generator and digital loop filter. The CRU can adjust the recovered clock phase with a resolution of 1.56 ps. Two sets of two-channel transceiver units were fabricated in 0.11-/spl mu/m CMOS on a single test chip. The transceiver unit size was 1.6 mm /spl times/ 2.6 mm. The Rx sensitivity was 120-mVp-p differential with a 70-ps phase margin for a common-mode voltage ranging from 0.6 to 1.0 V. The evaluated jitter tolerance curve met the OC-192 specification.     

A 128-kb FeRAM macro for contact/contactless smart-card microcontrollers

This paper describes a 128-kb FeRAM macro for smart-card microcontrollers. This macro, which was designed and fabricated using a 0.35-/spl mu/m three-metal CMOS and a Capacitor-on-Metal/Via-stacked-Plug (CMVP) process technology, is ideally suited for recent system LSIs such as smart-card microcontrollers. It has a flexible memory size ranging from 32 to 128 kb, a low consumption current of 0.3 mA, and endurance of more than 10/sup 8/ write/read cycles under a wide range of supply voltages, from 2.7 to 5.5 V. These characteristics, which are required of not only contact-type smart-card microcontrollers but also contactless-type ones, were achieved by using four newly developed circuit technologies: 1) a three-metal CMVP memory cell; 2) a voltage-regulating architecture; 3) a main/sub bitline and wordline structure; and 4) a dynamic-type offset sense amplifier.     

High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide

The 35 nm gate length CMOS devices with oxynitride gate dielectric and Ni salicide have been fabricated to study the feasibility of higher performance operation. Nitrogen concentration in gate oxynitride was optimized to reduce gate current I/sub g/ and to prevent boron penetration in the pFET. The thermal budget in the middle of the line (MOL) process was reduced enough to realize shallower junction depth in the S/D extension regions and to suppress gate poly-Si depletion. Finally, the current drives of 676 /spl mu/A//spl mu/m in nFET and 272 /spl mu/A//spl mu/m in pFET at V/sub dd/=0.85 V (at I/sub off/=100 nA//spl mu/m) were achieved and they are the best values for 35 nm gate length CMOS reported to date.     

自组织InAs/GaAs量子点的表面氮化研究

用低温光荧光(PL)和透射电子显微镜(TEM)研究了表面氮化自组织InAs/GaAs量子点的光学性能和微观结构。结果表明氮化后形成薄层的InAsN薄膜作为应变缓和层覆盖在量子点的表面,使得随着氮化时间的增加,InAs量子点的位错密度提高、尺寸变大、纵横比提高、发光波长变长、强度变低。