Two new low-power Full Adders based on majority-not gates

Two novel low-power 1-bit Full Adder cells are proposed in this paper. Both of them are based on majority-not gates, which are designed with new methods in each cell. The first cell is only composed of input capacitors and CMOS inverters, and the second one also takes advantage of a high-performance CMOS bridge circuit. These kinds of designs enjoy low power consumption, a high degree of regularity, and simplicity. Low power consumption is targeted in implementation of our designs. Eight state-of-the-art 1-bit Full Adders and two proposed Full Adders are simulated using 0.18 μm CMOS technology at many supply voltages. Simulation results demonstrate improvement in terms of power consumption and power-delay product (PDP).     

Ultra low power frequency divider for 2.45 GHz ZigBee frequency synthesizer

An ultra low power CMOS frequency divider whose modulus can be varied from 481 to 496 is presented. It has been customized to be used in 2.45 GHz Integer-N PLL frequency synthesizers utilized in ZigBee standard. Its based on swallow divider that replaces the swallow counter by a simple digital circuit in order to reduce power consumption and design complexity. Also a low power and high speed divide-by-7/8 is presented. Post layout simulation results exhibit 420 μW power consumption for 4 bit frequency divider in 2.45 GHz ISM frequency band that proves 40 % reduction compared to same previous works. All of the circuits have been designed in 0.18 μm TSMC CMOS technology with a single 1.8 V DC voltage supply.     

Novel direct designs for 3-input XOR function for low-power and high-speed applications

Novel direct designs for 3-input exclusive-OR (XOR) function at transistor level are proposed in this article. These designs are appropriate for low-power and high-speed applications. The critical path of the presented designs consists of only two pass-transistors, which causes low propagation delay. Neither complementary inputs, nor V _DD and ground exist in the basic structure of these designs. The proposed designs have low dynamic and short-circuit power consumptions and their internal nodes dissipate negligible leakage power, which leads to low average power consumption. Some effective approaches are presented for improving the performance, voltage levels, and the driving capability and lowering the number of transistors of the basic structure of the designs. All of the proposed designs and several classical and state-of-the-art 3-input XOR circuits are simulated in a realistic condition using HSPICE with 90 nm CMOS technology at six supply voltages, ranging from 1.3 V down to 0.8 V. The simulation results demonstrate that the proposed circuits are superior in terms of speed, power consumption and power-delay product (PDP) with respect to other designs.     

A new simple method for analysing of thermal noise in switched-capacitor filters

Thermal noise is one of the most important challenges in analogue integrated circuits design. This problem is more crucial in switched-capacitor (SC) filters due to the aliasing effect of wide-band thermal noise. In this article, a new simple method is proposed for estimating the power spectrum density of output thermal noise in SC filters, which have acceptable accuracy and short running time. In the proposed method, first using HSPICE simulator, accurate value of accumulated sampled noise on sampler capacitors in each clock state is achieved. Next, using difference equations of the SC filter, frequency response of the SC filter is shaped by time domain analysis. Based on the proposed method, a SC low-pass filter and a second-order SC band-pass filter are analysed. The results are validated by comparing to the previously measured data.     

A novel low-power full-adder cell for low voltage

This paper presents a novel low-power majority function-based 1-bit full adder that uses MOS capacitors (MOSCAP) in its structure. It can work reliably at low supply voltage. In this design, the time-consuming XOR gates are eliminated. The circuits being studied are optimized for energy efficiency at 0.18-μm CMOS process technology. The adder cell is compared with seven widely used adders based on power consumption, speed, power-delay product (PDP) and area efficiency. Intensive simulation runs on a Cadence environment and HSPICE show that the new adder has more than 11% in power savings over a conventional 28-transistor CMOS adder. In addition, it consumes 30% less power than transmission function adder (TFA) and is 1.11 times faster.     

Scenario Assessment of Streamflow Simulation and its Transition Probability in Future Periods Under Climate Change

The effect of climate change on water resources is an important challenge. To analyze the negative effects of this phenomenon and recommend adaptive measures, it is necessary to assess streamflow simulation scenarios and streamflow transition probabilities in future periods. This paper employs the HadCM3 (Hadley Centre Coupled Model, version 3) model to generate climate change scenarios in future periods (2010–2039, 2040–2069, and 2070–2099) and under A2 emission scenarios. By introducing climatic variable time series in future periods to the IHACRES (Identification of unit Hydrographs And Component flows from Rainfall, Evaporation and Streamflow data) hydrological model, long-term streamflow simulation scenarios are produced. By fitting statistically different distributions on runoff produced by using goodness-of-fit tests, the most appropriate statistical distribution for each month is chosen and relevant statistical parameters are extracted and compared with statistical parameters of runoff in the base period. Results show that long-term annual runoff average in the three future periods compared to the period 2000–1971 will decrease 22, 11, and 65 %, respectively. ?Despite the reduction in total runoff volume in future periods compared to the baseline period, the decrease is related to medium and high flows. In low flows, total runoff volumes for future periods compared to the baseline period will increase 47, 41, and 14 %, respectively. To further assess the impact of annual average runoff on flows, it is necessary to examine the correlation of time series using streamflow transition probabilities. To compare the streamflow transition probability in each of the future periods with base period streamflow in each month, streamflow is discretized and performance criteria are used. Results show a low coefficient of correlation and high error indicators.     

Multi-objective algorithms for the application mapping problem in heterogeneous multiprocessor embedded system design

The Journal of Supercomputing - Design at the Electronic System-Level tackles the increasing complexity of embedded systems by raising the level of abstraction in system specification and modeling....     

Flow separation control in open-channel bends

The investigation of fluid flow in sharp open-channel bends is key to controlling undesired sedimentation in natural river reaches. The difficulties are associated with controlling the flow separation in meanderings. Flow separation decreases the width of the flow, and consequently, the conveyance capacity while increasing erosion and mixing. This study proposes a novel approach to reduce the flow separation at the inner banks of sharp open-channel bends. Three-dimensional numerical experiments were conducted. To find the most reliable procedure, five turbulence models were examined. The employed numerical approach is formulated within the framework of the finite volume method and the volume of fluid (VOF) technique to solve the Navier–Stokes equations. Water levels and velocity profiles are obtained in different sections of the channel and are compared to experimental studies of a 90° sharp open-channel bend. A close agreement is observed using the RSM (Reynolds stress model) turbulence model. Moreover, the evaluation of acquired velocity profiles demonstrates that in a regular bend, the lowest velocity occurs near the inner bank, where it has a flow separation tendency. The same numerical procedure is employed to simulate water flow through a sharp converging open-channel bend. The measurements of velocity profiles and velocity vectors in the curved sections support the idea that decreasing the channel width considerably reduces the overall velocity variations in cross-sectional areas of the test case and is effective to control flow separation.     

Design and fabrication of a new high gain multilayer negative refractive index metamaterial antenna for X‐band applications

This article presents the design of a planar high gain and wideband antenna using a negative refractive index multilayer superstrate in the X‐band. This meta‐antenna is composed of a four‐layer superstrate placed on a conventional patch antenna. The structure resonates at a frequency of 9.4 GHz. Each layer of the metamaterial superstrate consists of a 7 × 7 array of electric‐field‐coupled resonators, with a negative refractive index of 8.66 to 11.83 GHz. The number of layers and the separation of superstrate layers are simulated and optimized. This metamaterial lens has significantly increased the gain of the patch antenna to 17.1 dBi. Measurements and simulation results proved about 10 dB improvement of the gain.