VLSI Implementation of Forward Error Control Technique for ATM Networks

In asynchronous transfer mode (ATM) networks, fixed length cells of 53 bytes are transmitted. A cell may be discarded during transmission due to buffer overflow or a detection of errors. Cell discarding seriously degrades transmission quality. The quality degradation can be reduced by employing efficient forward error control (FEC) to recover discarded cells. In this paper, we present the design and implementation of decoding equipment for FEC in ATM networks based on a single parity check (SPC) product code using very‐large‐scale integration (VLSI) technology. FEC allows the destination to reconstruct missing data cells by using redundant parity cells that the source adds to each block of data cells. The functionality of the design has been tested using the Model Sim 5.7cXE Simulation Package. The design has been implemented for a 5 ° 5 matrix of data cells in a Virtex‐E XCV 3200E FG1156 device. The simulation and synthesis results show that the decoding function can be completed in 81 clock cycles with an optimum clock of 56.8 MHz. A test bench was written to study the performance of the decoder, and the results are presented.     

Trellis and convolutional precoding for transmitter-based interference presubtraction

This paper studies the combination of practical trellis and convolution codes with Tomlinson-Harashima precoding (THP) for the presubtraction of multiuser interference that is known at the transmitter but not known at the receiver. It is well known that a straightforward application of THP suffers power, modulo, and shaping losses. This paper proposes generalizations of THP that recover some of these losses. At a high signal-to-noise ratio (SNR), the precoding loss is dominated by the shaping loss, which is about 1.53 dB. To recover shaping loss, a trellis-shaping technique is developed that takes into account the knowledge of a noncausal interfering sequence, rather than just the instantaneous interference. At rates of 2 and 3 bits per transmission, trellis shaping is shown to be able to recover almost all of the 1.53-dB shaping loss. At a low SNR, the precoding loss is dominated by power and modulo losses, which can be as large as 3-4 dB. To recover these losses, a technique that incorporates partial interference presubtraction (PIP) within convolutional decoding is developed. At rates of 0.5 and 0.25 bits per transmission, PIP is able to recover 1-1.5 dB of the power loss. For intermediate SNR channels, a combination of the two schemes is shown to recover both power and shaping losses.     

Towards deterministic downscaling of SMOS soil moisture using MODIS derived soil evaporative efficiency

A deterministic approach for downscaling ～ 40 km resolution Soil Moisture and Ocean Salinity (SMOS) observations is developed from 1 km resolution MODerate resolution Imaging Spectroradiometer (MODIS) data. To account for the lower soil moisture sensitivity of MODIS surface temperature compared to that of L-band brightness temperature, the disaggregation scale is fixed to 10 times the spatial resolution of MODIS thermal data (10 km). Four different analytic downscaling relationships are derived from MODIS and physically-based model predictions of soil evaporative efficiency. The four downscaling algorithms differ with regards to i) the assumed relationship (linear or nonlinear) between soil evaporative efficiency and near-surface soil moisture, and ii) the scale at which soil parameters are available (40 km or 10 km). The 1 km resolution airborne L-band brightness temperature from the National Airborne Field Experiment 2006 (NAFE'06) are used to generate a time series of eleven clear sky 40 km by 60 km near-surface soil moisture observations to represent SMOS pixels across the three-week experiment. The overall root mean square difference between downscaled and observed soil moisture varies between 1.4% v/v and 1.8% v/v depending on the downscaling algorithm used, with soil moisture values ranging from 0 to 15% v/v. The accuracy and robustness of the downscaling algorithms are discussed in terms of their assumptions and applicability to SMOS.     

Low-Power VLSI Implementation of the Inner Receiver for OFDM-Based WLAN Systems

In this paper, we propose low-power designs for the synchronizer and channel estimator units of the Inner Receiver in wireless local area network systems. The objective of the work is the optimization, with respect to power, area, and latency, of both the signal processing algorithms themselves and their implementation. Novel circuit design strategies have been employed to realize optimal hardware and power efficient architectures for the fast Fourier transform, arc tangent computation unit, numerically controlled oscillator, and the decimation filters. The use of multiple clock domains and clock gating reduces the power consumption further. These blocks have been integrated into an experimental digital baseband processor for the IEEE 802.11a standard implemented in the 0.25mum- 5-metal layer BiCMOS technology from Institute for High Performance Microelectronics.     

Energy-efficient video streaming over Bluetooth using rateless coding

Energy-efficient error control for IEEE 802.15.1 (Bluetooth) video communication is proposed. The scheme is based on block-oriented incremental redundancy provided by rateless coding and receiver feedback. Results are presented for time-sensitive video streaming applications under a Markovian channel model. When the proposed algorithm is compared to variations of Bluetooth forward error control, there are improvements of around 3 dB in received video quality and of over 10% in energy efficiency.     

A 0.9 V 92 dB Double-Sampled Switched-RC Delta-Sigma Audio ADC

A 0.9 V third-order double-sampled delta-sigma audio ADC is presented. A new method using a combination of a switched-RC technique and a floating switched-capacitor double-sampling configuration enabled low-voltage operation without clock boosting or bootstrapping. A three-level quantizer with simple dynamic element matching was used to improve linearity. The prototype IC implemented in a 0.13 CMOS process achieves 92 dB DR, 91 dB SNR and 89 dB SNDR in a 24 kHz audio signal bandwidth, while consuming 1.5 mW from a 0.9 V supply. The prototype operates from 0.65 V to 1.5 V supply with minimal performance degradation.