Low-frequency noise in modern bipolar transistors: impact ofintrinsic transistor and parasitic series resistances

In modern submicrometer transistors, the influence of the internal base and emitter series resistances, on both the I-V characteristics and the LF noise at higher bias currents, becomes important. In this paper expressions are presented for the LF noise in transistors, where the influence of the series resistances has been taken into account. The expressions have been compared with recent experimental results from the literature obtained from modern submicrometer (heterojunction) bipolar transistors. At low forward currents the LF noise in such transistors is determined by spontaneous fluctuations in the base and collector currents. In most transistors at higher forward currents, the parasitic series resistances and their noise become important     

Characterization of the cell leakage of a stacked trench capacitor(STT) cell

The cell leakage of a stacked trench capacitor (STT) cell has been investigated. The major leakage mechanisms of the STT are trench-to-trench leakage, trench junction leakage, and LOCOS isolation leakage. It is shown that compared to a conventional trench capacitor, the trench-to-trench leakage current is reduced and high punchthrough voltage is obtained. Therefore, the trench-to-trench spacing can be reduced 0.1 μm shorter than that of the trench capacitor. These reductions result from the STT structure itself. The surface leakage current, which is the dominant leakage current in the trench capacitor, does not flow in the STT. This paper also describes the effect of the sidewall damage caused by trench etching on the trench junction leakage. Reactive ion etching (RIE) produces deep levels just beneath the trench surface. But, the trench junction of the STT is not influenced by these deep levels because the trench surface is covered by a n^-diffused layer. This paper also investigates the relationship between the cell leakage and the retention time. At DRAM operation temperatures, LOCOS isolation leakage is dominant rather than trench junction leakage. Therefore, the deeper trench can increase the storage capacitance and improve the retention time     

In-plane transport properties of Si/Si1-xGexstructure and its FET performance by computer simulation

Transport properties of ungated Si/Si_1-xGe_x are studied by an ensemble Monte Carlo technique. The device performance is studied with a quantum hydrodynamic equation method using the Monte Carlo results. The phonon-scattering limited mobility is enhanced over bulk Si, and is found to reach 23000 cm²/Vs at 77 K and 4000 cm²/Vs at 300 K. The saturation velocity is increased slightly compared with the bulk value at both temperatures. A significant velocity overshoot, several times larger than the saturation velocity, is also found. In a typical modulation-doped field-effect-transistor, the calculated transconductance for a 0.18 μm gate device is found to be 300 mS/mm at 300 K. Velocity overshoot in the strained Si channel is observed, and is an important contribution to the transconductance. The inclusion of the quantum correction increases the total current by as much as 15%     

A semi-static complementary gain cell technology for sub-1 V supplyDRAM's

A new semi-static complementary gain cell for future low power DRAM's has been proposed and experimentally demonstrated. This gain cell consists of a write-transistor and its opposite conduction type read-transistor with a heating gate as a storage node which causes a shift in the threshold voltage. This gain cell provides a two orders of magnitude larger cell signal output and higher immunity to noise on the bitlines when compared with a conventional one-transistor DRAM cell without increasing the storage capacitance even at a supply voltage of 0.8 V. The 0.87 μm² cell size is achieved by using a 0.25 μm design rule with a polysilicon thin-film transistor built in the trench and phase shifted i-line lithography     

The effect of cosmic rays on the soft error rate of a DRAM atground level

This paper provides conclusive evidence that cosmic rays cause soft errors in commercial dynamic RAM (DRAM) chips at ground level. Cosmic-ray-induced soft errors in electronic components have long been a problem for the designers of satellites and spacecraft, but they have not generally been considered to be an important influence on memory chip soft error rate (SER) in terrestrial environments. In an experiment designed to determine the effect of cosmic radiation on the SER of a sample of DRAM chips at ground level, the SER of a large number of chips was measured at various locations and altitudes around the US: near sea level in Essex Junction, VT; 200 m underground in a Kansas salt mine; at an altitude of 1.6 km in Boulder, CO; and at 3.1 km in Leadville, CO. The results reported here show that even at sea level there is a significant component of the SER that can be attributed to the effects of cosmic rays, and that the magnitude of the effects increases dramatically at higher altitudes     

Functions and applications of monostable-bistable transition logicelements (MOBILE's) having multiple-input terminals

The MOBILE is a logic gate exploiting the monostable-bistable transition of a circuit that consists of two resonant tunneling transistors connected in series. It has several advantages including multiple inputs and multiple functions. This paper describes the output characteristics of multiple-input MOBILE's and discusses their applications. For a two-input MOBILE, it is demonstrated that both NAND and NOR operations are possible with the appropriate control voltage. This implies the possibility of a variable function logic gate. Furthermore, the threshold logic operations for a weighted sum of input signals are demonstrated for a three-input MOBILE with a weight ratio of 4:2:1. The applications of MOBILE's in parallel processing architectures such as cellular automata and cellular neural networks are discussed based on the above results. Circuit simulations using a simple model of resonant tunneling transistors successfully reproduce the basic characteristics of MOBILE's, and demonstrate the usefulness of MOBILE's in such applications     

Deep submicrometer super self-aligned Si bipolar technology with25.4 ps ECL

A new deep submicron double-poly self-aligned Si bipolar technology has been developed using a 0.3-μm design rule, a collector polysilicon trench electrode, and oxide-filled trench isolation. This technology is called “High-Performance Super Self-Aligned Process Technology” or HSST. 0.3-μm minimum patterning is achieved by electron-beam direct writing technology. The HSST bipolar transistor is 2.5 times smaller than the previous 1-μm SST-1B. Owing to its horizontal reduction and an f_T of 22.3 GHz at V_ce=1 V, the ECL gate attains 25.4 ps/G at 1.58 mA, which is a 30% improvement on the SST-1B. By including parasitic capacitances of the base polyelectrode and polyresistors, the ECL delay time is accurately simulated for low-power operation. It is shown that the HSST is a very promising technology for the development of future high-speed communication systems     

Measurement and modeling of self-heating in SOI nMOSFET's

Self-heating in SOI nMOSFET's is measured and modeled. Temperature rises in excess of 100 K are observed for SOI devices under static operating conditions. The measured temperature rise agrees well with the predictions of an analytical model and is a function of the silicon thickness, buried oxide thickness, and channel-metal contact separation. Under dynamic circuit conditions, the channel temperatures are much lower than predicted from the static power dissipation. This work provides the foundation for the extraction of device modeling parameters for dynamic operation (at constant temperature) from static device characterization data (where temperature varies widely). Self-heating does not greatly reduce the electromigration reliability of SOI circuits, but might influence SOI device design, e.g., requiring a thinner buried oxide layer for particular applications and scaled geometries     

Finite element computation of electromagnetic fields [hyperthermiatreatment]

A three dimensional finite element solution scheme is developed for numerically computing electromagnetically induced power depositions. The solution method is applicable to those problems for which it can be reasonably assumed that the magnetic permeability is homogeneous. The method employs an incident field/scattered field approach where the incident field is precalculated and used as the forcing function for the computation of the scattered field. A physically logical condition is used for the numerical boundary conditions to overcome the fact that electromagnetic problems are generally unbounded (i.e., the boundary condition is applied at infinity) but numerical models must have a boundary condition applied to some finite location. At that numerical boundary, an outgoing spherical wave is simulated. Finally, an alternate to a direct solution scheme is described. This alternate method, a preconditioned conjugate gradient solver, provides both a storage and CPU time advantage over direct solution methods. For example, a one-thousand fold decrease in CPU time was achieved for simple test cases. Unlike most iterative methods, the preconditioned conjugate gradient technique used has the important property of guaranteed convergence. Solutions obtained from this finite element method are compared to analytic solutions demonstrating that the solution method is second-order accurate     

Maximum and minimum return losses from a passive two-port networkterminated with a mismatched load

An analytical expression is derived for determining load-reflection coefficient phase-angle values that will lead to maximum and minimum return losses from a terminated two-port network. The expression is derived in terms of two-port network S-parameters and a load whose reflection-coefficient magnitude is a constant but can be any value greater than zero and less than or equal to unity. The equation is useful for cases where it is desirable to know how to position a load (1) to obtain maximum return loss for network-matching purposes or (2) to obtain minimum return loss for some types of reflector antenna applications. Two examples are given: One shows that for some types of reflector antennas with a mesh-type surface that is backed by another reflecting surface, a resonance phenomenon can occur and cause unexpectedly large dissipative losses (>30 dB) to occur. The other example shows that when a particular type of reflector antenna with a dielectric layer becomes wet from rain or condensation, large (>10 dB) signal losses can occur. For both examples, equations presented in this article were used to calculate the exact load-reflection coefficient phase values that led to worst-case return loss values. In practical situations, once the phenomenon is understood and predictable, steps can be taken to avoid these resonance regions