All‐Solution‐Processed Indium‐Free Transparent Composite Electrodes based on Ag Nanowire and Metal Oxide for Thin‐Film Solar Cells

Fully solution‐processed Al‐doped ZnO/silver nanowire (AgNW)/Al‐doped ZnO/ZnO multi‐stacked composite electrodes are introduced as a transparent, conductive window layer for thin‐film solar cells. Unlike conventional sol–gel synthetic pathways, a newly developed combustion reaction‐based sol–gel chemical approach allows dense and uniform composite electrodes at temperatures as low as 200 °C. The resulting composite layer exhibits high transmittance (93.4% at 550 nm) and low sheet resistance (11.3 Ω sq^‐1), which are far superior to those of other solution‐processed transparent electrodes and are comparable to their sputtered counterparts. Conductive atomic force microscopy reveals that the multi‐stacked metal‐oxide layers embedded with the AgNWs enhance the photocarrier collection efficiency by broadening the lateral conduction range. This as‐developed composite electrode is successfully applied in Cu(In_1‐x,Ga_x)S₂ (CIGS) thin‐film solar cells and exhibits a power conversion efficiency of 11.03%. The fully solution‐processed indium‐free composite films demonstrate not only good performance as transparent electrodes but also the potential for applications in various optoelectronic and photovoltaic devices as a cost‐effective and sustainable alternative electrode.     

Improvement of linewidth enhancement factor in 1.55-μmmultiple-quantum-well laser diodes

The improvement of the linewidth enhancement factor in complex-coupled laser diode (CC-LD), or loss-coupled, was confirmed by measuring the spontaneous emission spectra below threshold from the sidewall of laser diodes. In addition, the serial resistance of the device was measured. The linewidth enhancement factor is improved by the presence of a light absorbing InGaAs grating for loss coupled distributed-feedback (DFB) laser diode (LD). We report the comparison of the linewidth enhancement factors of Fabry-Perot (FP) LD, conventional DFB-LD, and loss coupled DFB-LDs     

1.04 GBd low EMI digital video interface system using small swingserial link technique

In a high-resolution flat panel system, a conventional interface that directly connects a liquid crystal display (LCD) controller to a flat panel cannot overcome the problems of excess EMI (electromagnetic interference) and power caused by full-swing transmission signals in parallel lines. This paper presents a high-speed digital video interface system implemented with a low-cost standard CMOS (complimentary metal-oxide-semiconductor) technology that can mitigate EMI and power problems in high-resolution flat panel display systems. The combined architecture of the high-speed, small number of parallel lines and low-voltage swing serial interface can support resolutions from VGA (640×480 pixels) up to XGA (1024×768 pixels) with significant power improvement and drastic EMI reduction. To support high-speed, low-voltage swing signaling and overcome channel-to-channel skew problems, a robust data recovery system is required. The proposed digital phase-locked loop enables robust skew-insensitive data recovery of up to 1.04 GBd     

Fast DCT algorithm with fewer multiplication stages

A novel fast DCT scheme with reduced multiplication stages and fewer additions and multiplications is proposed. The proposed algorithm is structured so that most multiplications tend to be performed at the final stage, which reduces the propagation error that could occur in the fixed-point computation. Minimisation of the multiplication stages can further decrease the error     

Capacity of large hybrid erasure networks with random node distribution

The Gupta–Kumar’s nearest-neighbor multihop routing with/without infrastructure support achieves the optimal capacity scaling in a large erasure network in which n wireless nodes and m relay stations are regularly placed. In this paper, a capacity scaling law is completely characterized for an infrastructure-supported erasure network where n wireless nodes are randomly distributed, which is a more feasible scenario. We use two fundamental path-loss attenuation models (i.e., exponential and polynomial power-laws) to suitably model an erasure probability. To show our achievability result, the multihop routing via percolation highway is used and the corresponding lower bounds on the total capacity scaling are derived. Cut-set upper bounds on the capacity scaling are also derived. Our result indicates that, under the random erasure network model with infrastructure support, the achievable scheme based on the percolation highway routing is order-optimal within a polylogarithmic factor of n for all values of m.     

35-nm Zigzag T-Gate $hbox{In}_{0.52}hbox{Al}_{0.48} hbox{As/In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ Metamorphic GaAs HEMTs With an Ultrahigh $f_{max}$ of 520 GHz

Metamorphic GaAs high electron mobility transistors (mHEMTs) with the highest-f _max reported to date are presented here. The 35-nm zigzag T-gate In_0.52Al_0.48As/In_0.53Ga_0.47As metamorphic GaAs HEMTs show f _maxof 520 GHz, f _T of 440 GHz, and maximum transconductance (g _m) of 1100 mS/mm at a drain current of 333 mA/mm. The combinations of f _max and f _T are the highest data yet reported for mHEMTs. These devices are promising candidates for aggressively scaled sub-35-nm T-gate mHEMTs.     

A single-chip storage LSI for home networks

Network direct attached storage (NDAS) is a network storage architecture that allows direct attachment of existing ATA/ATAPI devices to Ethernet without a separate server. Unlike other architectures such as NAS, SAN, and USB mass storage, no server computer intervenes between the storage and the client hosts. We describe an NDAS disk controller (NDC) amenable to low-cost single-chip implementation that processes a simplified L3/L4 protocol and converts commands between ATA/ATAPI and Ethernet, while the remaining complex tasks are performed by remote hosts. Unlike NAS architectures that use TCP/IP, NDAS uses a TCP-like lean protocol that lends itself well to high-performance hardware realization. Thanks to the simple NDAS architecture and protocol, an NDC implemented on a single 4 mm /spl times/ 4 mm chip in 0.18 /spl mu/m CMOS technology achieves a maximum throughput of 55 Mbytes/s on gigabit Ethernet, which is comparable to that of a high-performance disk locally attached to a host computer.     

W-band divide-by-3 frequency divider using 0.1 /spl mu/m InAlAs/InGaAs metamorphic HEMT technology

A W-band divide-by-3 frequency divider with wide bandwidth and low power dissipation is presented using harmonic injection-locking technique. A cascode FET is employed for a self-oscillating second-harmonic mixer which is injection-locked by third-harmonic input to obtain the division order of three. The fabricated frequency divider using 0.1 /spl mu/m GaAs metamorphic HEMT technology shows superior performance such as large bandwidth of 6.1 GHz around 83.1 GHz (7.3%) under small DC power consumption of 12 mW.     

Novel configurations of planar multilayer magic-T usingmicrostrip-slotline transitions

Novel configurations of microwave planar magic-T suitable for microwave integrated circuits (MICs) and monolithic MICs are described. They consist of microstrip and slotline T-junctions coupled by microstrip-slotline transitions. Since via-hole processing is not encountered, they are especially applicable to multilayer MICs. Derived equivalent network models are used efficiently for the design of the corresponding multilayer microstrip magic-T. Measured data and numerical simulations showing good amplitude and phase characteristics over an octave operating bandwidth validate the proposed configurations of planar magic-T