Numerical Analysis of the Boundary Scattering Effect on Transport Properties in Bi-Sb Nanowires

In this study, we have numerically analyzed the transport properties of Bi-Sb nanowires, taking into account wire boundary scattering. Wire boundary scattering slightly decreased the Seebeck coefficient of Bi-Sb nanowires. This effect is due to the observation that boundary scattering and the mobility ratio of L-point electrons to T-point holes in the nanowires are smaller than those in bulk Bi-Sb because the wire boundary scattering suppresses the mobilities of L-point electrons and heavy holes. The largest Seebeck coefficient for all wire diameters was obtained when the Sb concentration was 5 at.%. The effective mass approached zero near 5 at.% Sb, and the small effective mass led to a large subband shift in each band. Thus, a small effective mass enhances the quantum effect at a fixed wire diameter, even if wire boundary scattering is taken into account.     

The process dependence on positive bias temperature aginginstability of p+(B) polysilicon-gate MOS devices

During positive bias temperature (BT) aging, a large number of interface traps on p⁺(B) polysilicon MOS devices are generated in the upper half of the bandgap without an increase in the charges trapped in the gate oxide. The increase in interface traps can be reduced by processes which exclude the hydrogen included during fabrication. The increase in the interface-state density is explained as follows. The generation of the interface traps is caused by hydrogen ions reaching at the SiO₂/Si interface through the gate oxide from the polysilicon-gate electrode. The hydrogen ions combine with activated boron and are released from the boron under positive BT aging. The increase in interface traps is formulated by equations which are derived from the above model     

Dynamic bandwidth control of the virtual path in an asynchronoustransfer mode network

The virtual path concept has several valuable features to construct an economical and efficient asynchronous transfer mode (ATM) network. One of them is bandwidth control which affords transmission efficiency improvement through statistical sharing of capacity. An effective bandwidth control algorithm and its calculated performance are described. Network performance with the algorithm is evaluated, and the bandwidth control is shown to successfully improve network transmission efficiency with only a slight increase in processing load compared to the fixed bandwidth scheme. A method is also proposed to equalize call loss probability for each virtual path. The effectiveness of the method is demonstrated by analysis     

A 1.5-V full-swing BiCMOS logic circuit

A BiCMOS logic circuit applicable to sub-2-V digital circuits has been developed. A transiently saturated full-swing BiCMOS (TS-FS-BiCMOS) logic circuit operates twice as fast as CMOS at 1.5-V supply. A newly developed transient-saturation technique, with which bipolar transistors saturate only during switching periods, is the key to sub-2-V operation because a high-speed full-swing operation is achieved to remove the voltage loss due to the base-emitter turn-on voltage. Both small load dependence and small fan-in dependence of gate delay time are attained with this technique. A two-input gate fabricated with 0.3-μm BiCMOS technology verifies the performance advantage of TS-FS-BiCMOS over other BiCMOS circuits and CMOS at sub 2-V supply     

Network architecture for optical path transport networks

This paper proposes a new layered transport network architecture on which the WDM optical path network can be effectively created. The optical path network will play a key role in the development of the transport network that will realize the bandwidth-abundant B-ISDN. This paper extends the layered transport network architecture described in ITU-T Recommendation G.803 which is applied in existing SDH networks. First, we elucidate an application example of WDM optical path networks. Next, we propose a new layered architecture for WDM-based transport networks that retains maximum commonality with the layered architectures developed for existing B-ISDN networks. The proposed architecture is composed of circuit layer networks, electrical path layer networks, optical layer networks, and physical media (fiber) networks. The optical layer is divided into an optical path layer and an optical section layer. The optical path layer accommodates electrical paths. Optical section layer networks are divided into optical multiplex section (OMS) layer networks and optical repeater section (ORS) layer networks. The OMS layer network is concerned with the end-to-end transfer of information between locations transferring or terminating optical paths, whereas the ORS layer is concerned with the transfer of information between individual optical repeaters. Finally, a detailed functional block model of WDM optical path networks, the function allocation of each layer, and an optical transport module (OTM) are developed     

A side-wall transfer-transistor cell (SWATT cell) for highlyreliable multi-level NAND EEPROMs

A multi-level NAND Flash memory cell, using a new Side-WAll Transfer-Transistor (SWATT) structure, has been developed for a high performance and low bit cost Flash EEPROM. With the SWATT cell, a relatively wide threshold voltage (V_th) distribution of about 1.1 V is sufficient for a 4-level memory cell in contrast to a narrow 0.6 V distribution that is required for a conventional 4-level NAND cell. The key technology that allows this wide V_th distribution is the Transfer Transistor which is located at the side wall of the Shallow Trench Isolation (STI) region and is connected in parallel with the floating gate transistor. During read, the Transfer Transistors of the unselected cells (connected in series with the selected cell) function as pass transistors. So, even if the V_th of the unselected floating gate transistor is higher than the control gate voltage, the unselected cell will be in the ON state. As a result, the V_th distribution of the floating gate transistor can be wider and the programming can be faster because the number of program/verify cycles can be reduced. Furthermore, the SWATT cell results in a very small cell size of 0.57 μm² for a 0.35 μm rule. Thus, the SWATT cell combines a small cell size with a multi-level scheme to realize a very low bit cost. This paper describes the process technology and the device performance of the SWATT cell, which can be used to realize NAND EEPROM's of 512 Mbit and beyond     

Automatic extraction and measurement of leukocyte motion inmicrovessels using spatiotemporal image analysis

This paper describes a computer vision system for the automatic extraction and velocity measurement of moving leukocytes that adhere to microvessel walls from a sequence of images. The motion of these leukocytes can be visualized as motion along the wall contours. The authors use the constraint that the leukocytes move along the vessel wall contours to generate a spatiotemporal image, and the leukocyte motion is then extracted using the methods of spatiotemporal image analysis. The generated spatiotemporal image is processed by a special-purpose orientation-selective filter and a subsequent grouping process newly developed for this application. The orientation-selective filter is designed by considering the particular properties of the spatiotemporal image in this application in order to enhance only the traces of leukocytes. In the subsequent grouping process, leukocyte trace segments are selected and grouped among all the segments obtained by simple thresholding and skeletonizing operations. The authors show experimentally that the proposed method can stably extract leukocyte motion     

A Thermoplastic Gel Electrolyte for Stable Quasi‐Solid‐State Dye‐Sensitized Solar Cells

Dye‐sensitized solar cells (DSSCs) are receiving considerable attention as low‐cost alternatives to conventional solar cells. In DSSCs based on liquid electrolytes, a photoelectric efficiency of 11 % has been achieved, but potential problems in sealing the cells and the low long‐term stability of these systems have impeded their practical use. Here, we present a thermoplastic gel electrolyte (TPGE) as an alternative to the liquid electrolytes used in DSSCs. The TPGE exhibits a thermoplastic character, high conductivity, long‐term stability, and can be prepared by a simple and convenient protocol. The viscosity, conductivity, and phase state of the TPGE can be controlled by tuning the composition. Using 40 wt % poly(ethylene glycol) (PEG) as the polymeric host, 60 wt % propylene carbonate (PC) as the solvent, and 0.65 M KI and 0.065 M I₂ as the ionic conductors, a TPGE with a conductivity of 2.61 mS cm^–2 is prepared. Based on this TPGE, a DSSC is fabricated with an overall light‐to‐electrical‐energy conversion efficiency of 7.22 % under 100 mW cm^–2 irradiation. The present findings should accelerate the widespread use of DSSCs.     

DNA Computing Boosted by a Cationic Copolymer

The huge information storage capability of DNA and its ability to self‐assemble can be harnessed to enable massively parallel computing in a small space. DNA‐based logic gates are designed that rely on DNA strand displacement reactions; however, computation is slow due to time‐consuming DNA reassembly processes and prone to failure as DNA is susceptible to degradation by nucleases and under certain solution conditions. Here, it is shown that the presence of a cationic copolymer boosts the speed of DNA logic gate operations that involve multiple and parallel strand displacement reactions. Two kinds of DNA molecular operations, one based on a translator gate and one on a seesaw gate, are successfully enhanced by the copolymer without tuning of computing conditions or DNA sequences. The copolymer markedly reduces operation times from hours to minutes. Moreover, the copolymer enhances nuclease resistance.     

Growth of large-diameter ZnTe single crystals by liquid-encapsulated melt growth methods

The 80-mm-diameter ZnTe single crystals were successfully obtained by the liquid-encapsulated Kyropoulos (LEK) method. Both 〈100〉- and 〈110〉-oriented single crystals were reproducibly grown by using ZnTe seed crystals. Furthermore, 80-mm-diameter, 〈100〉 and 〈110〉 ZnTe single crystals were obtained by the pulling method. The etch pit densities (EPDs) of the grown crystals by the LEK and pulling methods were lower than 10,000 cm⁻². The strain in the grown crystals by the pulling method was lower than that of LEK crystals.