Enhancement mode InP MISFET's with sulfide passivation andphoto-CVD grown P3N5 gate insulators

High performance enhancement mode InP MISFET's have been successfully fabricated by using the sulfide passivation for lower interface states and with photo-CVD grown P₃N₅ film used as gate insulator. The MISFET's thus fabricated exhibited exhibited pinch-off behavior with essentially no hysteresis. Furthermore the device showed a superior stability of drain current. Specifically under the gate bias of 2 V for 10⁴ seconds the room temperature drain current was shown to reduce from the initial value merely by 2.9% at the drain voltage of 4 V. The effective electron mobility and extrinsic transconductance are found to be about 2300 cm ²/V·s and 2.7 mS/mm, respectively. The capacitance-voltage characteristics of the sulfide passivated InP MIS diodes show little hysteresis and the minimum density of interface trap states as low as 2.6×10¹⁴/cm² eV has been attained     

A fully distributed power control algorithm for cellular mobilesystems

Several distributed power control algorithms that can achieve carrier-to-interference ratio (CIR) balancing with probability one have been proposed previously for cellular mobile systems. In these algorithms, only local information is used to adjust transmitting power. However, a normalization procedure is required in each iteration to determine transmitting power and, thus, these algorithms are not fully distributed. In this paper, we present a distributed power control algorithm which does not need the normalization procedure. We show that the proposed algorithm can achieve CIR balancing with probability one. Moreover, numerical results reveal our proposed scheme performs better than the algorithm presented in Grandhi et al. [1994]. The excellent performance and the fully distributed property make our proposed algorithm a good choice for cellular mobile systems     

Quantitative NMR spectroscopy by matrix pencil methods

The matrix pencil (MP) method, based on the singular value decomposition (SVD), is applied to quantitative NMR spectroscopy. Its relationship to other SVD-based methods is also presented. Simulations and applications are given to demonstrate the capability of superior performance.©1993 John Wiley & Sons Inc     

Simple approximations of the DC flux influence on the core losspower electronic ferrites and their use in design of magnetic components

The effect of DC flux on the core loss is examined for the practical range of power and frequency. Relevant core loss equations are derived and applied to an optimization algorithm to determine the minimum core loss at a given ratio of s (DC flux density to AC peak flux density). It has been found that the curves of hysteresis loss density versus the ratio of s exhibit a peak at a critical ratio. Below or above this critical ratio, the loss density decreases drastically. On the other hand, the curves of eddy-current loss density versus the ratio of s exhibits a minimum point at a critical ratio. Below or above this critical ratio, the loss density increases gradually     

Solder engineering for optoelectronic packaging

In addition to providing electrical connections, solder is useful in the formation of passive, precision alignments for optoelectronic packaging. Different designs have demonstrated micrometer-level alignment accuracies, and the aligned structures are becoming more and more complex. Solder engineering has been successfully introduced into the field of optoelectronics, and it is expected to be applied to many other areas demanding low-cost, precision alignments.     

Degradation of junction leakage in devices subjected to gateoxidation in nitrous oxide [MOS transistors]

Nitrided gate oxides offer several electrical and reliability advantages over conventional oxides and also provide a good barrier against impurity diffusion. Oxidation in nitrous oxide (N₂O) has been very successful in overcoming some of the problems associated with nitridation in ammonia. The authors have observed that the extent of N₂O oxidation has a strong detrimental effect on the drain leakage current of MOS transistors in the off state. This phenomenon has been identified to be caused by an increase in the active area junction leakage current