基于路灯杆基站的规划建模研究

对路灯杆基站的应用场合原则、选址模型、天馈系统规划设计进行了详细的说明,并通过应用案例证明了关于路灯杆基站的规划设计方法在打造联通精品网络的工作中有着深远的推广意义。     

基于空间语义模型的高分辨率遥感图像目标检测方法

该文提出一种基于空间语义模型的方法,用于高分辨率遥感图像复杂场景中典型地物目标的自动检测。该方法通过分割获取图像对象,引入主题模型统计对象的多维特征,提高了对象特性描述的精度。在此基础上,对图像中有意义的地物目标及它们之间的空间关系建模表达和定量计算,通过获取场景的语义解析树,辅助实现对复杂地物目标的准确提取和定位。在测试数据集上的实验结果表明,该文方法具有较高的智能化程度和较强的稳定性。     

时分噪声调频干扰性能分析与验证

时分噪声调频干扰是一种常用的多目标干扰样式,对其性能的分析研究具有重要意义。构建了时分噪声调频干扰信号的产生模型,统计了不同的干扰重复周期、有效调制带宽和占空比下时分噪声调频干扰信号的功率和干扰带宽,分析出这些参数对时分噪声调频干扰信号功率和干扰带宽的影响,指出了关于脉冲信号带宽认识上的误区。对时分多目标干扰模拟设备生成的信号进行了测试,验证了相关结论。     

Hierarchical Ordered Dual‐Mesoporous Polypyrrole/Graphene Nanosheets as Bi‐Functional Active Materials for High‐Performance Planar Integrated System of Micro‐Supercapacitor and Gas Sensor

Planar integrated systems of micro‐supercapacitors (MSCs) and sensors are of profound importance for 3C electronics, but usually appear poor in compatibility due to the complex connections of device units with multiple mono‐functional materials. Herein, 2D hierarchical ordered dual‐mesoporous polypyrrole/graphene (DM‐PG) nanosheets are developed as bi‐functional active materials for a novel prototype planar integrated system of MSC and NH₃ sensor. Owing to effective coupling of conductive graphene and high‐sensitive pseudocapacitive polypyrrole, well‐defined dual‐mesopores of ≈7 and ≈18 nm, hierarchical mesoporous network, and large surface area of 112 m² g^?1, the resultant DM‐PG nanosheets exhibit extraordinary sensing response to NH₃ as low as 200 ppb, exceptional selectivity toward NH₃ that is much higher than other volatile organic compounds, and outstanding capacitance of 376 F g^?1 at 1 mV s^?1 for supercapacitors, simultaneously surpassing single‐mesoporous and non‐mesoporous counterparts. Importantly, the bi‐functional DM‐PG‐based MSC‐sensor integrated system represents rapid and stable response exposed to 10–40 ppm of NH₃ after only charging for 100 s, remarkable sensitivity of NH₃ detection that is close to DM‐PG‐based MSC‐free sensor, impressive flexibility with ≈82% of initial response value even at 180°, and enhanced overall compatibility, thereby holding great promise for ultrathin, miniaturized, body‐attachable, and portable detection of NH₃.     

Analysis of a secure conference scheme for mobile communication

Dynamic participation is a feature of the secure conference schemes that allows new conferees to join and the old conferees to leave. The conferees who have left should not be able to decrypt the secure conference communication anymore. A secure conference scheme with dynamic participation was proposed in M.S. Hwang and W.P. Yang (1995) and later it was modified with the self-encryption mechanism in K.F. Hwang and C.C. Chang (2003) for a better performance. In this paper we analyze both the original scheme and the modified version. We show that both of them are subject to the active and passive attacks presented in this paper. Our active attack works in the way that a colluding group of attackers can still obtain the conference key even after they all leave the conference. The passive attack does not need any attacker to ever participate the conference. The conference key can be compromised with a large probability as long as the number of conferees is large.     

Metal gate-HfO/sub 2/ MOS structures on GaAs substrate with and without Si interlayer

In this letter, we studied the effects of post-deposition anneal (PDA) time and Si interface control layer (ICL) on the electrical characteristics of the MOS capacitor with high-/spl kappa/ (HfO/sub 2/) material on GaAs. Thin equivalent oxide thickness (EOT<3 nm) with excellent capacitance-voltage (C-V) characteristics has been obtained. The thickness of the Si ICL and PDA time were correlated with C-V characteristics. It was found that high temperature Si ICL deposition and longer PDA time at 600/spl deg/C improved the C-V shape, leakage current, and especially frequency dispersion (<5%).     

Numerical analysis on compliance and electrical behavior of multi-copper-column flip-chip interconnects for wafer-level packaging

This paper presents modeling and simulation results of a modified copper-column-based flip-chip interconnect with ultrafine pitch for wafer-level packaging, and the process and prototyping procedure are described as well. This interconnect consists of multiple copper columns which are electrically in parallel and supporting a solder bump. A simple analytical model has been developed for correlation between the interconnect geometry and the thermal fatigue life. In comparison to the conventional single-copper-column (SCC) interconnects, numerical analysis reveals that the multi-copper-column (MCC) interconnect features enhanced compliances and, hence, higher thermomechanical reliability, while the associated electrical parasitics (R, L, and C) at dc and moderate frequencies are still kept low. Parametric studies reveal the effects of geometric parameters of MCC interconnects on both compliances and electrical parasitics, which in turn facilitate design optimization for best performance. By using coplanar waveguides (CPWs) as feed lines on both chip and package substrate, a high-frequency (up to 40 GHz) S-parameter analysis is conducted to investigate the transmission characteristics of the MCC interconnects within various scenarios which combines various interconnect pitches and common chip and package substrates. An equivalent lumped circuit model is proposed and the circuit parameters (R, L, C, and G) are obtained throughout a broad frequency range. Good agreement is achieved for the transmission characteristics between the equivalent lumped circuit model and direct simulation results.     

一种基于小波变换的信号恒虚警率检测方法

基于噪声和信号在不同尺度下的特性,引入小波域中噪声置信度概念,利用删除技术CM(Censored Method)估计小波域中的噪声功率水平,采用软阈值处理,提出一种信号恒虚警检测方法。理论分析表明该方法在高斯噪声背景下具有恒虚警率特性,对不同杂波背景下的信号处理结果表明了该方法的鲁棒性。     

EOS中透明传输问题分析及解决方案

在SDH网络上传送以太网业务(EOS,Ethernet over SDH)具有巨大的优势。EOS能利用现有的SDH网络为以太网业务传送提供完善的OAM性能。在EOS系统中,透明传输以太网业务有非常重要的作用。本文详细分析了时钟、故障传递、流量控制和自协商相关的透明传输问题,相应的解决方案也同时提出。     

Ultra-Low Power Pipeline Structure Exploiting Noncritical Stage with Circuit-Level Timing Speculation

With the increase of the clock frequency and silicon integration, power aware computing has become a critical concern in the design of the embedded processor and system-on-chip (SoC). Dynamic voltage scaling (DVS) is an effective method for low-power designs. However, traditional DVS methods have two deficiencies. First, they have a conservative safety margin which is not necessary for most of the time. Second, they are exclusively concerned with the critical stage and ignore the significant potential free slack time of the noncritical stage. These factors lead to a large amount of power waste. In this paper, a novel pipeline structure with ultra-low power consumption is proposed. It cuts off the safety margin and takes use of the noncritical stages at the same time. A prototype pipeline is designed in 0.13 m technology and analyzed. The result shows that a large amount of energy can be saved by using this structure. Compared with the fixed voltage case, 50% of the energy can be saved, and with respect to the traditional adaptive voltage scaling design, 37.8% of the energy can be saved.