High-performance and power-efficient CMOS comparators

Several design techniques for high-performance and power-efficient CMOS comparators are proposed. First, the comparator is based on the priority-encoding (PE) algorithm, and the dynamic circuit technique developed specifically for the priority encoder can be applied. Second, the PE function and the subsequent logic functions are merged and efficiently realized in the multiple output domino logic (MODL) to result in a shortened logic depth. The circuit in MODL CMOS is also compact and power efficient because few transistors are needed. Third, the multilevel look-ahead technique is used to shorten the path of priority-token propagation. Finally, the circuit is realized with a latch-based two-stage pipelined structure, and the comparison function is partitioned into two parts, with each part executed in each half of the clock cycle in a delay-balanced manner. Post-layout simulation results show that a 64-b comparator designed with the proposed techniques in a 3-V 0.6-/spl mu/m CMOS technology is 16% faster, 50% smaller, and 79% more power efficient as compared with the all-n-transistor comparator, which is the fastest among the conventional comparators. Measurement results of the test chip conform with simulation results and prove the feasibility of the proposed techniques.     

A 1.5-V 45-mW direct-conversion WCDMA receiver IC in 0.13-/spl mu/m CMOS

A 2-GHz direct-conversion receiver for wide-band code division multiple access (WCDMA) is presented. It includes two low-noise amplifiers (LNAs), an I/Q demodulator, and two sixth-order baseband channel select filters with programmable gain. Quadrature local oscillator (LO) signals are generated on chip in a frequency divider flip-flop. An external interstage filter between the LNAs rejects transmitter leakage to relax demodulator linearity requirements. A low-voltage demodulator topology improves linearity as well as demodulator output pole accuracy. The active-RC baseband filter uses a programmable servo loop for offset compensation and provides an adjacent channel rejection of 39 dB. Programmable gain over 71-dB range in 1-dB steps is merged with the filter to maximize dynamic range. An automatic on-chip frequency calibration scheme provides better than 1.5% corner frequency accuracy. The receiver is integrated in a 0.13-/spl mu/m CMOS process with metal-insulator-metal (MIM) capacitors. Measured receiver performance includes a 6.5-dB noise figure, IIP2 of +27 dBm, and IIP3 of -8.6 dBm. Power consumption is 45 mW.     

掌握油气生产发展规律 提高自动化应用水平

油气生产的自动化过程控制是转变生产方式,发展油气生产依靠的主要科学技术之一.结合油气生产发展的特征,全面总结了中国石油近几年自动化技术应用取得的成绩,针对不同的生产特征,确定了自动化控制系统的不同功能和构成特点,提出了自动化系统应用中存在的问题和发展方向.     

不同级配对微表处混和料性能的影响

微表处技术是一种性能优良的路面养护技术。首先检验了微表处用原材料的技术指标,在满足规范的要求下选择了三种不同级配,并对三种不同级配的微表处混和料的使用性能进行了比较。     

RI/VI联用测定聚乙烯相对分子质量及其分布

150℃测试温度下，以1，2，4-三氯苯为溶剂，采用示差折光指数器，毛细管黏度计双检测器联用凝胶渗透色谱技术测定了聚乙烯的相对分子质量及其分布。与常规凝胶渗透色谱法对比，该方法不仅能直接得到聚乙烯较精确的相对分子质量和分布形态，同时可以得到聚乙烯的特性黏数分布。     

新会计准则对会计准则质量的影响

年初,国家财政部发布了新的会计准则,这是中国会计准则建设史上的重大事件。新会计准则体现出会计准则质量的几个重要标准,提高了中国会计准则的质量。同时,分析新会计准则质量方面仍存在的一些不足。     

基于PC机群的大地电磁Occam反演并行计算研究

Occam反演以其稳定收敛和不依赖于初始模型的特性被广泛应用于大地电磁数据的处理，但偏导数矩阵的计算和拉格朗日乘子的求取导致大量的模型正演，使得反演速度较低。为此，研究了用基于PC机群的并行计算来解决这一问题的方法。首先对Occam反演方法进行了阐述；然后，分析了反演方法中各计算耗费的时间，提出对约占计算量90％的偏导数和拉格朗日乘子进行并行计算的思想，即偏导数计算采用频点计算一级的大粒度并行，拉格朗日乘子扫描和一维搜索分别采用弘值计算一级的大粒度并行和频点计算一级的小粒度并行；给出了并行计算的实现方法，即在PC机群上，利用主一从编程模式实现Occam反演的整体并行计算。在计算中，采用任务组合方式，减少了通信量，较好地实现了负载均衡。在4节点PC机群上，对应于拉格朗日乘子的扫描和一维搜索方式，整体加速比分别达到3．36和2．83。     

催化精馏合成N-异丙基苯胺

在Joback基团贡献法估算反应的G ibbs函数的基础上,得到了异丙醇与苯胺合成N-异丙基苯胺的平衡常数与反应温度的关系式。研究了回流比、异丙醇与苯胺的摩尔比、塔釜操作温度、苯胺进料口位置距塔顶的距离对异丙醇与苯胺催化精馏合成N-异丙基苯胺的影响,确定了适宜的工艺条件:回流比2.5~3.5、异丙醇与苯胺的摩尔比1.5、塔釜操作温度223℃、苯胺进料口位置距塔顶300~400mm。在优化条件下,苯胺的转化率可达到99%,N-异丙基苯胺的选择性可达到99.5%,N-异丙基苯胺的质量分数可稳定在98.8%以上。     

Analysis and architecture design of variable block-size motion estimation for H.264/AVC

Variable block-size motion estimation (VBSME) has become an important video coding technique, but it increases the difficulty of hardware design. In this paper, we use inter-/intra-level classification and various data flows to analyze the impact of supporting VBSME in different hardware architectures. Furthermore, we propose two hardware architectures that can support traditional fixed block-size motion estimation as well as VBSME with less chip area overhead compared to previous approaches. By broadcasting reference pixel rows and propagating partial sums of absolute differences (SADs), the first design has the fewer reference pixel registers and a shorter critical path. The second design utilizes a two-dimensional distortion array and one adder tree with the reference buffer that can maximize the data reuse between successive searching candidates. The first design is suitable for low resolution or a small search range, and the second design has advantages of supporting a high degree of parallelism and VBSME. Finally, we propose an eight-parallel SAD tree with a shared reference buffer for H.264/AVC integer motion estimation (IME). Its processing ability is eight times of the single SAD tree, but the reference buffer size is only doubled. Moreover, the most critical issue of H.264 IME, which is huge memory bandwidth, is overcome. We are able to save 99.9% off-chip memory bandwidth and 99.22% on-chip memory bandwidth. We demonstrate a 720-p, 30-fps solution at 108 MHz with 330.2k gate count and 208k bits on-chip memory.