Second-Order Consensus of Multi-agent Systems via Periodically Intermittent Pinning Control

In this paper, we investigate the leader-following consensus of second-order multi-agent systems with nonlinear dynamics and time delay by employing periodically intermittent pinning control. All member agents and the virtual leader share the same nonlinear dynamics relating to the velocity and delayed velocity information. Based on Lyapunov stability theory, we obtain a novel criterion that is independent of the time delay and control width to guarantee the second-order consensus of multi-agent systems with time delay and periodically intermittent controllers. Numerical simulations are presented to illustrate the theoretical results.     

Unfalsified Adaptive PID Control for Time-Varying Systems Using a Fading Memory Cost Function

In this paper, we present a new cost function based on fading memory and time-window in order to decrease the influence of old data in unfalsified adaptive control applications, where the plant varies slowly or changes suddenly with time. Based on the unfalsified adaptive PID control, and the linear increasing cost-level algorithm (LICLA) switching algorithm, the new cost function can guarantee that the switching will stop and the system is stable. A systematic analysis of the system stabilization has been given. The simulation results show that without any prior knowledge of the system plant, when the current controller inserted in the system cannot guarantee the stability of the system, the cost function with a fading memory can detect the instability more quickly and then switch into a new stabilizing controller faster than the original cost function.     

Robust Stability and $$H_{\infty }$$ Control of Discrete-Time Uncertain Impulsive Systems with Time-Varying Delay

This paper considers the robust stability and \(H_{\infty }\) control problems for a class of discrete-time uncertain impulsive systems with time-varying delay. Sufficient conditions for the robust stability, stabilization and \(H_\infty \) control of the considered systems are developed. Some numerical examples are presented to show the effectiveness of the theoretical results.     

An Improved-Linearity,Single-Stage Variable-Gain Amplifier Using Current Squarer for Wider Gain Range

A novel single-stage variable-gain amplifier (VGA) based on transconductance \(g_{m}\)-ratio amplifier is analyzed and designed with wider linear-in-dB gain range and improved linearity. The variable-gain amplifier proposed here consists of an exponential control block, a current squarer and an amplifier block with both input and load degeneration. With the help of current squarer which gets square function of the output current from exponential control block, the VGA achieves the maximum linear gain range in single stage. Current squarer is proposed, which is designed with compensation technique to minimize the second-order effect caused by carrier mobility reduction in short channel MOSFET. To avoid the poor linearity performance of the \(g_{{m}}\)-ratio amplifiers, the distortion is analyzed and the linearity is improved by applying input and load degenerating technique. At the same power consumption, the input 1 dB compression point can be improved by nearly 8.78 dB. Simulation results show that the VGA can provide a gain variation range of 64.09 dB (from \(-35.59\) to 28.5 dB) with a 3-dB bandwidth from 47 to 640 MHz. The circuit consumes the maximum power 3.5 mW from a 1.8-V supply.     

3-state BTL closed-loop PWM Class D amplifiers

One of the shortcomings of a number of Class D amplifiers (CDAs) designs is their susceptibility to supply noise, quantified by Power Supply Rejection Ratio (PSRR). Reported investigations thereto to-date remain incomplete/over-simplified, particularly the assumption that the AC ground is noise-less and a simplified fully-differential integrator model. In this paper, the effect of supply noise in the AC ground to PSRR is analytically investigated, and the associated analytical expressions derived. Of specific interest, the analysis is applied to the ubiquitous 3-state Bridge-tied-load (BTL) closed-loop PWM CDA, taking into consideration not only the effect of the non-ideal AC ground, but also the effect of the resistor and capacitor mismatch based on a realistic fully-differential integrator model. Further, the PSRR analysis of 3-state BTL closed-loop CDAs has to date been limited to the single-feedback topology and in this paper, extended to the double-feedback topology. These analyses and derived equations herein are useful as they provide valuable insights to CDA designers into the PSRR mechanisms—for example, the counter-intuitive observation that the CDA with 1st-order integrators provides similar or better PSRR than the CDA with 2nd-order integrators if both CDAs are designed to the same carrier attenuation—including the effect of various circuit parameters, and ensuing trade-offs. The derived analytical expressions are verified by means of HSPICE simulations and on the basis of practical measurements on discretely-realized CDAs.     

Applying SMT-based verification to hardware/software partitioning in embedded systems

When performing hardware/software co-design for embedded systems, the problem of which functions of the system should be implemented in hardware (HW) or in software (SW) emerges. This problem is known as HW/SW partitioning. Over the last 10 years, a significant research effort has been carried out in this area. In this paper, we present two new approaches to solve the HW/SW partitioning problem by using verification techniques based on satisfiability modulo theories (SMT). We compare the results using the traditional technique of integer linear programming, specifically binary integer programming and a modern method of optimization by genetic algorithm. The experimental results show that SMT-based verification techniques can be effective in particular cases to solve the HW/SW partition problem optimally using a state-of-the-art model checker based on SMT solvers, when compared against traditional techniques.     

Optimal Non-Invasive Fault Classification Model for Packaged Ceramic Tile Quality Monitoring Using MMW Imaging

Millimeter wave (MMW) frequency has emerged as an efficient tool for different stand-off imaging applications. In this paper, we have dealt with a novel MMW imaging application, i.e., non-invasive packaged goods quality estimation for industrial quality monitoring applications. An active MMW imaging radar operating at 60 GHz has been ingeniously designed for concealed fault estimation. Ceramic tiles covered with commonly used packaging cardboard were used as concealed targets for undercover fault classification. A comparison of computer vision-based state-of-the-art feature extraction techniques, viz, discrete Fourier transform (DFT), wavelet transform (WT), principal component analysis (PCA), gray level co-occurrence texture (GLCM), and histogram of oriented gradient (HOG) has been done with respect to their efficient and differentiable feature vector generation capability for undercover target fault classification. An extensive number of experiments were performed with different ceramic tile fault configurations, viz., vertical crack, horizontal crack, random crack, diagonal crack along with the non-faulty tiles. Further, an independent algorithm validation was done demonstrating classification accuracy: 80, 86.67, 73.33, and 93.33 % for DFT, WT, PCA, GLCM, and HOG feature-based artificial neural network (ANN) classifier models, respectively. Classification results show good capability for HOG feature extraction technique towards non-destructive quality inspection with appreciably low false alarm as compared to other techniques. Thereby, a robust and optimal image feature-based neural network classification model has been proposed for non-invasive, automatic fault monitoring for a financially and commercially competent industrial growth.     

Ultra-compact 1 × 8 Channel terahertz Wave Power Splitter

Relying on 1?×?2 photonic crystal waveguide and photonic crystal resonator, a compact eight-channel terahertz wave power splitter is proposed. The mechanism of such a device is further theoretically analyzed and numerically investigated with the aid of the plane wave expansion method and the finite-difference time-domain method. With an appropriate design, the proposed power splitter can split the input terahertz wave energy equally into eight output ports at the frequency of 0.667 THz. Furthermore, the total size of the present device is of 4.33 mm?×?3.74 mm. Due to its small size, the multi-channel terahertz wave power splitter has practical applications in the terahertz wave integrated circuit fields.     

CMOS-Compatible Room-Temperature Rectifier Toward Terahertz Radiation Detection

In this paper, we present a new rectifying device, compatible with the technology of CMOS image sensors, suitable for implementing a direct-conversion detector operating at room temperature for operation at up to terahertz frequencies. The rectifying device can be obtained by introducing some simple modifications of the charge-storage well in conventional CMOS integrated circuits, making the proposed solution easy to integrate with the existing imaging systems. The rectifying device is combined with the different elements of the detector, composed of a 3D high-performance antenna and a charge-storage well. In particular, its position just below the edge of the 3D antenna takes maximum advantage of the high electric field concentrated by the antenna itself. In addition, the proposed structure ensures the integrity of the charge-storage well of the detector. In the structure, it is not necessary to use very scaled and costly technological nodes, since the CMOS transistor only provides the necessary integrated readout electronics. On-wafer measurements of RF characteristics of the designed junction are reported and discussed. The overall performances of the entire detector in terms of noise equivalent power (NEP) are evaluated by combining low-frequency measurements of the rectifier with numerical simulations of the 3D antenna and the semiconductor structure at 1 THz, allowing prediction of the achievable NEP.