Sub-50 nm P-channel FinFET

High-performance PMOSFETs with sub-50-nm gate-length are reported. A self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short-channel effects. This vertical double-gate SOI MOSFET features: 1) a transistor channel which is formed on the vertical surfaces of an ultrathin Si fin and controlled by gate electrodes formed on both sides of the fin; 2) two gates which are self-aligned to each other and to the source/drain (S/D) regions; 3) raised S/D regions; and 4) a short (50 nm) Si fin to maintain quasi-planar topology for ease of fabrication. The 45-nm gate-length p-channel FinFET showed an I_dsat of 820 μA/μm at V_ds=V_gs=1.2 V and T _ox=2.5 mm. Devices showed good performance down to a gate-length of 18 nm. Excellent short-channel behavior was observed. The fin thickness (corresponding to twice the body thickness) is found to be critical for suppressing the short-channel effects. Simulations indicate that the FinFET structure can work down to 10 nm gate length. Thus, the FinFET is a very promising structure for scaling CMOS beyond 50 nm     

A 76-mm2 8-Mb chain ferroelectric memory

This paper demonstrates the first 8-Mb chain ferroelectric RAM (chain FeRAM) with 0,25-μm 2-metal CMOS technology. A small die of 76 mm² and a high average cell/chip area efficiency of 57.4 % have been realized by introducing not only chain architecture but also four new techniques: 1) a one-pitch shift cell realizes small cell size of 5.2 μm²; 2) a new hierarchical wordline architecture reduces row-decoder and plate-driver areas without an extra metal layer; 3) a small-area dummy cell scheme reduces dummy capacitor size to 1/3 of the conventional one; and 4) a new array activation scheme reduces dataline and second amplifier areas. As a result, the chain architecture with these new techniques reduces die size to 65% of that of the conventional FeRAM. Moreover a ferroelectric capacitor overdrive scheme enables sufficient polarization switching, without overbias memory cell array. This scheme lowers the minimum operation voltage by 0.23 V, and enables 2.5-V V_dd operation. Thanks to fast cell plateline drive of chain architecture, the 8-Mb chain FeRAM has achieved the fastest random access time, 40 ns, and read/write cycle time, 70 ns, at 3.0 V so far reported     

Formation of uniform GaAs multi-atomic steps with 20–30 nm periodicity and related structures on vicinal (111)B planes by MBE

We studied morphology of GaAs surfaces and the transport properties of two-dimensional electron gas (2DEG) on vicinal (111)B planes. Multi-atomic steps (MASs) are found on the vicinal (111)B facet grown by molecular beam epitaxy, which will affect electron transport on the facet. We also studied how the morphology of GaAs epilayers on vicinal (111)B substrates depends on growth conditions, especially on the As₄ flux. The uniformity of MASs on the substrates have been improved and smooth surfaces were obtained when the GaAs was grown with high As₄ flux, providing step periodicity of 20 nm. The channel resistance of the 2DEG perpendicular to the MASs is reduced drastically with this smooth morphology. These findings are valuable not only for fabricating quantum devices on the (111)B facets but also those on the vicinal (111)B substrates.     

An experimental 1.5-V 64-Mb DRAM

Low-voltage circuit technologies for higher-density dynamic RAMs (DRAMs) and their application to an experimental 64-Mb DRAM with a 1.5-V internal operating voltage are presented. A complementary current sensing scheme is proposed to reduce data transmission delay. A speed improvement of 20 ns was achieved when utilizing a 1.5-V power supply. An accurate and speed-enhanced half-V_CC voltage generator with a current-mirror amplifier and tri-state buffer is proposed. With it, a response time reduction of about 1.5 decades was realized. A word-line driver with a charge-pump circuit was developed to achieve a high boost ratio. A ratio of about 1.8 was obtained from a power supply voltage as low as 1.0 V. A 1.28 μm² crown-shaped stacked-capacitor (CROWN) cell was also made to ensure a sufficient storage charge and to minimize data-line interference noise. An experimental 1.5 V 64 Mb DRAM was designed and fabricated with these technologies and 0.3 μm electron-beam lithography. A typical access time of 70 ns was obtained, and a further reduction of 50 ns is expected based on simulation results. Thus, a high-speed performance, comparable to that of 16-Mb DRAMs, can be achieved with a typical power dissipation of 44 mW, one tenth that of 16-Mb DRAMs. This indicates that a low-voltage battery operation is a promising target for future DRAMs     

NRZ operation at 40 Gb/s of a compact module containing an MQW electroabsorption modulator integrated with a DFB laser

NRZ operation at 40 Gb/s has been successfully performed using a very compact module of a multiple-quantum-well (MQW) electroabsorption modulator integrated with a distributed-feedback (DFB) laser. While the DFB laser is injected with a constant current, the integrated MQW electroabsorption modulator is driven with a 10-Gb/s electrical NRZ signal. A clearly opened eye diagram has been observed in the modulated light from the modulator. And a receiver sensitivity of -27.2 dBm at 10/sup -9/ has been experimentally confirmed in the bit-error-rate (BER) performance.     

High-performance C60 and picene thin film field-effect transistors with conducting polymer electrodes in bottom contact structure

C₆₀ and picene thin film field-effect transistors (FETs) in bottom contact structure have been fabricated with poly(3,4-ethylenedioxythiophene): poly(styrenesulfonate) (PEDOT:PSS) electrodes for a realization of mechanical flexible organic FETs. The C₆₀ thin film FETs showed n-channel enhancement-type characteristics with the field-effect mobility μ value of 0.41 cm² V^?1 s^?1, while the picene thin film FET showed p-channel enhancement-type characteristics with the μ of 0.61 cm² V^?1 s^?1. The μ values recorded for C₆₀ and picene thin film FETs are comparable to those for C₆₀ and picene thin film FETs with Au electrodes.     

1.3 /spl mu/m InGaAsN vertical cavity surface emitting lasers grown by MOCVD

The first InGaAsN VCSELs grown by MOCVD with CW lasing wavelength longer than 1.3 /spl mu/m are reported. The devices were of conventional p-i-n structure with doped DBR mirrors. CW lasing up to 65/spl deg/C was observed, with a maximum output power at room temperature of 0.8 mW for multimode devices and nearly 0.3 mW for single-mode devices.     

Compositional design of Pb(Zr, Ti)O3 for highly reliableferroelectric memories

We have investigated Pb(Zr,Ti)O₃ (PZT) film composition suitable for highly reliable ferroelectric RAM (FeRAM) application. To obtain a wide operational margin for 2T/2C (two transistors and two capacitors) FeRAMs, the PZT film capacitor is needed to have a low coercive voltage (V_c) and a high dielectric constant on the polarization switching (ϵ_S) and a low dielectric constant on the nonswitching (ϵ_N), or essentially a large ϵ_S/ϵ_N ratio. Concerning the B-site composition in the perovskite structure, it is found that lowering the Zr/Ti ratio from 47/53 to Ti-richer ones increases the ratio of ϵ_S/ϵ_N as a positive effect on the wide operational margin, but increased V_c as a negative effect. Taking the balance of these factors into consideration, it is concluded that an optimum composition, such as Zr/Ti=30/70, provides the maximum operational margin. The A-site composition, on the other hand, affects the long-term reliability of a PZT capacitor. The endurance to the fatigue and imprint are enhanced by reduction of the Pb-excess and dope of La in the A-site. A La-doped PZT (Zr/Ti =30/70) capacitor is successfully integrated to the 8 kbit FeRAM macro with double-layer Al wiring to confirm the feasibility of this capacitor