Two new low-power Full Adders based on majority-not gates

Two novel low-power 1-bit Full Adder cells are proposed in this paper. Both of them are based on majority-not gates, which are designed with new methods in each cell. The first cell is only composed of input capacitors and CMOS inverters, and the second one also takes advantage of a high-performance CMOS bridge circuit. These kinds of designs enjoy low power consumption, a high degree of regularity, and simplicity. Low power consumption is targeted in implementation of our designs. Eight state-of-the-art 1-bit Full Adders and two proposed Full Adders are simulated using 0.18 μm CMOS technology at many supply voltages. Simulation results demonstrate improvement in terms of power consumption and power-delay product (PDP).     

Shallow and Undoped Germanium Quantum Wells: A Playground for Spin and Hybrid Quantum Technology

Buried‐channel semiconductor heterostructures are an archetype material platform for the fabrication of gated semiconductor quantum devices. Sharp confinement potential is obtained by positioning the channel near the surface; however, nearby surface states degrade the electrical properties of the starting material. Here, a 2D hole gas of high mobility (5 × 10⁵ cm² V^?1 s^?1) is demonstrated in a very shallow strained germanium (Ge) channel, which is located only 22 nm below the surface. The top‐gate of a dopant‐less field effect transistor controls the channel carrier density confined in an undoped Ge/SiGe heterostructure with reduced background contamination, sharp interfaces, and high uniformity. The high mobility leads to mean free paths ≈ 6 µm, setting new benchmarks for holes in shallow field effect transistors. The high mobility, along with a percolation density of 1.2 × 10¹¹cm^?2, light effective mass (0.09m_e), and high effective g‐factor (up to 9.2) highlight the potential of undoped Ge/SiGe as a low‐disorder material platform for hybrid quantum technologies.     

Analog to digital converter for high density neural signal recording front-end in 90 nm

High-fidelity recording of neural signals requires varying levels of signal gain to capture low-amplitude single-unit activity in the presence of high-amplitude population activity. A floating-point approach has been used to widen the dynamic range of analog-to-digital converters (ADC) designed for this application. In this paper we present an ADC, designed for multi-channel, portable neural signal recording systems. To achieve low power consumption, small die area and wide dynamic range, an ADC based on a time-based algorithm, combined with a floating-point pipelined structure has been designed and simulated. A conventional variable-gain amplifier (VGA) stage has been eliminated in favor of a reference-current in a time-based ADC architecture. The 12-b pipelined time-based floating-point ADC has been designed with a 7-b mantissa and an exponent that provides an additional 5 bits of dynamic range. The mantissa is determined by a uniform 7-b pipelined time-based analog to digital converter. The ADC chip was designed and simulated in a 90 nm CMOS process, which occupies an active area of 360 μm × 550 μm, and consumes 7.8 μW at 1.2 V in full-scale conversion.     

Reference frame modification techniques for temporal and spatial scalability

Compressed video is usually transmitted over channels which are not necessarily error free. Channel errors can result in a mismatch between the encoder and the decoder, and because of the predictive structures used in video coding, the errors will propagate both temporally and spatially. Consequently, the quality of the received video at the decoder may degrade significantly. In order to improve the quality of the received video, several error resilient methods have been proposed. In this paper, the introduced mismatch is reduced by modifying the prediction structure and forming a more robust reference frame. The proposed technique combines error robustness of previous Intra coded blocks, better prediction achieved using the previous reference frame, and exponential decay of error propagation caused by the leaky prediction. This technique was examined with the scalable extension of H.264/AVC. Furthermore, the technique was also used in combination with random Intra refresh and error resilience mode decision techniques to achieve better robustness. Simulation results show the effectiveness of our scheme, especially for medium and high motion sequences.     

On the necessary and sufficient requirement of a CIOQ switch to emulate an Output Queued switch

There has been much interest to emulate the behavior of Output Queued switches. The early result of such attempts was reported by Prabhakar and McKeown using the CIOQ switches with speedup factor of 4. Subsequently, Stoica and Zhang and independently Chuang et al. showed that a speedup of 2 in conjunction with their scheduling schemes would be sufficient for CIOQ switches to emulate Output Queued switches.Additionally, Chuang et al. showed that in “Average Sense” a speedup of 2?1/N is necessary and sufficient for CIOQ to emulate Output Queued switch behavior.Our paper reports that in the “Strict Sense” a speedup of 2 is both necessary and sufficient. We show this requirement using examples for 2x2 and 3x3 switches. Then, with a constructed traffic pattern, it is proved that in the “Strict Sense” a speedup of 2 is necessary to emulate the behavior of an Output Queued switch for any switch size N.Combining this result with the previous scheduling schemes, we conclude that in the “Strict Sense”, a speedup of 2 is the necessary and sufficient condition to emulate the behavior of an Output Queued switch, using a CIOQ switch.Additionally, easing the assumptions and allowing the packet segmentation, it is shown that the speedup requirement to emulate the behavior of an Output Queued switch can be reduced to values even smaller than 2?1/N. For this case a lower bound of 3/2 and an upper bound of 2 is proved.     

CPTR: conditional probability tree based routing in opportunistic networks

In opportunistic networks due to the inconsistency of the nodes link, routing is carried out dynamically and we cannot use proactive routes. In these networks, nodes use opportunities gained based on store-carry-forward patterns to forward messages. Every node that receives a message when it encounters another node makes decision regarding the forwarding or not forwarding the node encountered. In some previous methods, the recognition of whether encounter with current node is considered as an appropriate opportunity or not has been carried out based on the comparison of the probability of carrier node and the node encountered. In these methods, if the message is delivered to the encountered node, a better opportunity would be lost. To fight with this challenge we have posed CPTR method by using conditional probability tree method through which in addition to the probability of the delivery of carrier and encountered nodes’ message delivery, the opportunities for after encounter will be involved in messages’ forwarding. Results of simulation showed that the proposed method can improve the ratio of delivery and delay of message delivery compared to other similar methods in networks with limited buffer.     

MDP-Based Network Selection Scheme by Genetic Algorithm and Simulated Annealing for Vertical-Handover in Heterogeneous Wireless Networks

The hybrid algorithm for real-time vertical handover using different objective functions has been presented to find the optimal network to connect with a good quality of service in accordance with the user’s preferences. Markov processes are widely used in performance modelling of wireless and mobile communication systems. We address the problem of optimal wireless network selection during vertical handover, based on the received information, by embedding the decision problem in a Markov decision process (MDP) with genetic algorithm (GA), we use GA to find a set of optimal decisions that ensures the best trade-off between QoS based on their priority level. Then, we emerge improved genetic algorithm (IGA) with simulated annealing (SA) as leading methods for search and optimization problems in heterogeneous wireless networks. We formulate the vertical handoff decision problem as a MDP, with the objectives of maximizing the expected total reward and minimizing average number of handoffs. A reward function is constructed to assess the QoS during each connection, and the AHP method are applied in an iterative way, by which we can work out a stationary deterministic handoff decision policy. As it is, the characteristics of the current mobile devices recommend using fast and efficient algorithms to provide solutions near to real-time. These constraints have moved us to develop intelligent algorithm that avoid the slow and massive computations. This paper compares the formulation and results of five recent optimization algorithms: artificial bee colony, GA, differential evolution, particle swarm optimization and hybrid of (GA–SA). Simulation results indicated that choosing the SA rules would minimize the cost function, and also that, the IGA–SA algorithm could decrease the number of unnecessary handovers, and thereby prevent the ‘Ping-Pong’ effect.     

Using Markov Learning Utilization Model for Resource Allocation in Cloud of Thing Network

Wireless Personal Communications - The integration of the Internet of Things (IoT) and cloud environment has led to the creation of Cloud of Things, which has given rise to new challenges in IoT...     

Low-power CMOS distributed amplifier using new cascade gain cell for high and low gain modes

A CMOS distributed amplifier (DA) with low-power and flat and high power gain (S₂₁) is presented. In order to decrease noise figure (NF) an RL terminating network used for the gate transmission line instead of single resistance. Besides, a flat and high S₂₁ is achieved by using the proposed cascade gain cell consist of a cascode-stage with bandwidth extension capacitor. In the high-gain mode, under operation condition of V _dd  = 1.2 V and the overall current consumption of 7.8 mA, simulation result shown that the DA consumed 9.4 mW and achieved a flat and high S₂₁ of 20.5 ± 0.5 dB with an average NF of 6.5 dB over the 11 GHz band of interest, one of the best reported flat gain performances for a CMOS UWB DA. In the low-gain mode, the DA achieved average S₂₁ of 15.5 ± 0.25 dB and an average NF of 6.6 dB with low power consumption (P_DC) of 3.6 mW, the lowest P_DC ever reported for a CMOS DA or LNA with an average gain better than 10 dB.