A Branching Time Temporal Framework for Quantitative Reasoning

Temporal logics such as Computation Tree Logic (CTL) and Linear Temporal Logic (LTL) have become popular for specifying temporal properties over a wide variety of planning and verification problems. In this paper we work towards building a generalized framework for automated reasoning based on temporal logics. We present a powerful extension of CTL with first-order quantification over the set of reachable states for reasoning about extremal properties of weighted labeled transition systems in general. The proposed logic, which we call Weighted Quantified Computation Tree Logic (WQCTL), captures the essential elements common to the domain of planning and verification problems and can thereby be used as an effective specification language in both domains. We show that in spite of the rich, expressive power of the logic, we are able to evaluate WQCTL formulas in time polynomial in the size of the state space times the length of the formula. Wepresent experimental results on the WQCTL verifier.     

In vivo cytogenetic studies on mice exposed to acesulfame-K--a non-nutritive sweetener

Acesulfame-K, a sweetening agent, was evaluated in vivo for its genotoxic and clastogenic potentials. Swiss albino male mice were exposed to the compound by gavage. Bone marrow cells isolated from femora were analysed for chromosome aberrations. Doses of 15, 30, 60, 450, 1500 and 2250 mg of acesulfame-K/kg body weight induced a positive dose-dependent significant clastogenicity (trend test alpha < 0.05). These doses were within the no-toxic-effect levels (1.5-3 g/kg body weight in rats) reported by the Joint Expert Committee for Food Additives of the World Health Organization and the Food and Agriculture Organization of the United Nations. In view of the present significant in vivo mammalian genotoxicity data, acesulfame-K should be used with caution.     

Quantified Computation Tree Logic

Computation Tree Logic (CTL) is one of the most syntactically elegant and computationally attractive temporal logics for branching time model checking. In this paper, we observe that while CTL can be verified in time polynomial in the size of the state space times the length of the formula, there is a large set of reachability properties which cannot be expressed in CTL, but can still be verified in polynomial time. We present a powerful extension of CTL with first-order quantification over sets of reachable states. The extended logic, QCTL, preserves the syntactic elegance of CTL while enhancing its expressive power significantly. We show that QCTL model checking is PSPACE-complete in general, but has a rich fragment (containing CTL) which can be checked in polynomial time. We show that this fragment is significantly more expressive than CTL while preserving the syntactic beauty of CTL.     

Hole mobility enhancement in strained-Si p-MOSFETs under high vertical field

The growth of a high quality, step-graded lattice-relaxed SiGe buffer layer on a Si(100) substrate is investigated. p-MOSFETs were fabricated on strained-Si grown on top of the above layer. Carrier confinement at the type-II strained-Si/SiGe buffer interface is observed clearly from the device transconductance and C-V measurements. At high vertical field, compared to bulk silicon, the channel mobility of the strained-Si device with x=0.18 is found to be about 40% and 200% higher at 300 K and 77 K respectively. Measurements on transconductance enhancement are also reported. Data at 77 K provide evidence of two channels and a large enhancement of mobility at high transverse field.     

A low power scheduling scheme with resources operating at multiplevoltages

This paper presents resource and latency constrained scheduling algorithms to minimize power/energy consumption when the resources operate at multiple voltages (5 V, 3.3 V, 2.4 V, and 1.5 V). The proposed algorithms are based on efficient distribution of slack among the nodes in the data-flow graph. The distribution procedure tries to implement the minimum energy relation derived using the Lagrange multiplier method in an iterative fashion. Two algorithms are proposed, 1) a low complexity O(n²) algorithm and 2) a high complexity O(n² log(L)) algorithm, where n is the number of nodes and L is the latency. Experiments with some HLS benchmark examples show that the proposed algorithms achieve significant power/energy reduction. For instance, when the latency constraint is 1.5 times the critical path delay, the average reduction is 39%     

Simulation of single phase non-Newtonian flow characteristics of heavy crude oil through horizontal pipelines

The effect of diameter, velocity, and temperature on flow properties of heavy crude oil in three horizontal pipelines using computational fluid dynamics (CFD) was studied. The flow characteristics were simulated by using CFD software, ANSYS Fluent 6.2. The mesh geometry of the pipelines having inner diameter of 1, 1.5, and 2 inch were created by using Gambit 2.4.6. From grid independent study, 221, 365 mesh sizes were selected for simulation. The CFD ANSYS Fluent 6.2 Solver predicted the flow phenomena, pressure, pressure drop, wall shear stress, shear strain rate, and friction factor. A good agreement between experimental and CFD simulated values was obtained.     

Stability Analysis of Laminated Soft Core Sandwich Plates Using Higher Order Zig-Zag Plate Theory

C₀ finite element model based on higher order zig-zag plate theory is used to study the stability analysis of laminated sandwich plates. The in-plane displacement field is obtained by superposing a global cubically varying displacement field on a zig-zag linearly varying displacement field with different slope in each layer. The transverse displacement assumes to have a quadratic variation within the core and constant in the faces. The conditions regarding transverse shear stress at layer interfaces and top and bottom are satisfied. Numerical examples covering different features of laminated sandwich plates are presented to illustrate the accuracy of the model.     

FPGA Architecture for 2D Discrete Fourier Transform Based on 2D Decomposition for Large-sized Data

Applications based on Discrete Fourier Transforms (DFT) are extensively used in several areas of signal and digital image processing. Of particular interest is the two-dimensional (2D) DFT which is more computation- and bandwidth-intensive than the one-dimensional (1D) DFT. Traditionally, a 2D DFT is computed using Row-Column (RC) decomposition, where 1D DFTs are computed along the rows followed by 1D DFTs along the columns. Both application specific and reconfigurable hardware have utilized this scheme for high-performance implementations of 2D DFT. However, architectures based on RC decomposition are not efficient for large input size data due to memory bandwidth constraints. In this paper, we propose an efficient architecture to implement 2D DFT for large-sized input data based on a novel 2D decomposition algorithm. This architecture achieves very high throughput by exploiting the inherent parallelism due to the algorithm decomposition and by utilizing the row-wise burst access pattern of the external memory. A high throughput memory interface has been designed to enable maximum utilization of the memory bandwidth. In addition, an automatic system generator is provided for mapping this architecture onto a reconfigurable platform of Xilinx Virtex-5 devices. For a 2K ×2K input size, the proposed architecture is 1.96 times faster than RC decomposition based implementation under the same memory constraints, and also outperforms other existing implementations.