Very Low Voltage MOS Translinear Loops Based on Flipped Voltage Followers

A novel technique for operating MOS Translinear loops at very low supply voltages is described, based on the use of Flipped Voltage Followers for biasing the loops. The resulting topologies, suited to standard CMOS processes, can be successfully applied to a varied repertory of low-voltage analog circuits, such as squarers, multipliers, filters, oscillators, and RMS-DC converters. Measurement results for a geometric-mean and a squarer/divider circuit demonstrate on silicon the usefulness of this technique.     

An energy efficient joint localization and synchronization solution for wireless sensor networks using unmanned aerial vehicle

Localization and synchronization are fundamental services for many applications in wireless sensor networks (WSNs), since it is often required to know the sensor nodes’ position and global time to relate a given event detection to a specific location and time. However, the localization and synchronization tasks are often performed after the sensor nodes’ deployment on the sensor field. Since manual configuration of sensor nodes is usually an impractical activity, it is necessary to rely on specific algorithms to solve both localization and clock synchronization problems of sensor nodes. With this in mind, in this work we propose a joint solution for the problem of 3D localization and time synchronization in WSNs using an unmanned aerial vehicle (UAV). A UAV equipped with GPS flies over the sensor field broadcasting its geographical position. Therefore, sensor nodes are able to estimate their geographical position and global time without the need of equipping them with a GPS device. Through simulation experiments, we show that our proposed joint solution reduces time synchronization and localization errors as well as energy consumption when compared to solutions found in the literature.     

Highly linear micropower class AB current mirrors using Quasi-Floating Gate transistors

A design approach to achieve low-voltage micropower class AB CMOS cascode current mirrors is presented. Both class AB operation and dynamic cascode biasing are based on the use of Quasi-Floating Gate transistors. They allow high linearity for large signal currents and accurately set quiescent currents without requiring extra power consumption or supply voltage requirements. Measurement results show that dynamic cascode biasing allows a wider input range and a linearity improvement of more than 23 dB with respect to the use of conventional biasing. A THD value better than −35 dB is measured for input amplitudes up to 100 times the bias currents. Two class AB current mirror topologies are proposed, with slightly different ways to achieve class AB operation and dynamic biasing. The proposed current mirrors, fabricated in a 0.5 µm CMOS technology, are able to operate with a supply voltage of 1.2 V and a quiescent power consumption of only 36 µW, using a silicon area <0.025 mm².     

New Alternatives to the Estimation Problem in Hardware-Software Codesign of Complex Embedded Systems: The H.261 Video Co-dec Case Study

As Codesign problems become larger and more realistic, the required time to estimate their solutions turns into an important bottleneck. This paper presents a new approach to improve the traditional estimation techniques, in order to avoid this drawback. The presented method has been successfully tested on a large experimental benchmark, attaining quality levels close to those provided by the Synopsys Behavioral Compiler. Finally, a case study based on the standard H.261 video co-dec is described, proving the convenience of the technique on real-life situations. The obtained results show a significant improvement in the process time, while keeping the good precision and fidelity levels that the traditional estimation models usually offer.     

A 0.8 μm CMOS testable switched-capacitor filter for video frequency applications

This paper presents the design of a fifth-order low-pass elliptic filter that employs a parallel connection of two all-pass sections to satisfy specifications commonly used in video frequency applications. Operating with a sampling frequency of 16 MHz, the IC prototype was implemented in a standard double-poly CMOS 0.8 μm process. The experimental verification showed a passband frequency deviation smaller than 0.08 dB up to the passband edge frequency of 3.4 MHz, and an output noise power of 0.97 ${\mu {\rm V}_{\rm RMS}}/{\sqrt {Hz}}This paper presents the design of a fifth-order low-pass elliptic filter that employs a parallel connection of two all-pass sections to satisfy specifications commonly used in video frequency applications. Operating with a sampling frequency of 16 MHz, the IC prototype was implemented in a standard double-poly CMOS 0.8 μm process. The experimental verification showed a passband frequency deviation smaller than 0.08 dB up to the passband edge frequency of 3.4 MHz, and an output noise power of 0.97 , resulting in a dynamic range of 49.1 dB. The filter structure enables multiple fault detection and suits modern automated testing configurations to allow accurate estimation of the actually implemented transfer function parameters, an issue of increasing importance in VLSI circuit design. The relative area required for testing the fifth-order filter is only 8% of the total filter area, and decreases as the filter order increases. Jorge Morales Ca?ive was born in Cienfuegos, Cuba, in 1963. He received the B.Sc. and M.Sc. degrees from the Technical University of San Petersburg, Russia, in 1986 and 1988, respectively, and the D.Sc. degree from the Federal University of Rio de Janeiro, Brazil, in 1991, all in electrical engineering. From 1988 to 1994, he worked at CEADEN, in Havana, Cuba, on the development of nuclear equipments. From 1994 to 1997, he worked at INOR, in Havana, Cuba, on the research and development of acquisition systems and image processing for nuclear medicine. His research interests are in the areas of analog and digital signal processing. Antonio Petraglia (S’89-M’91-SM’99) received the Engineer and M.Sc. degrees from the Federal University of Rio de Janeiro (UFRJ), Brazil, in 1977 and 1982, respectively, and the Ph.D. degree from the University of California, Santa Barbara (UCSB), in 1991, all in electrical engineering. In 1979, he joined the Faculty of UFRJ as an Associate Professor of electrical engineering, where he served as a Co-Chair in the Department of Electronic Engineering from 1982 to 1984. During the second semester of 1991, he was a post-Doctoral researcher with the Department of Electrical and Computer Engineering at UCSB. Since 1992 he has been on the faculty of the Program for Post-Graduate Engineering at UFRJ, where in 1997 he established the Laboratory for the Processing of Analog and Digital Signals. From March 2001 through March 2002 he was a Visiting Scholar with the Electrical Engineering Department at the University of California, Los Angeles. He has been involved in teaching and research activities in the areas of analog and digital signal processing, and in mixed analog-digital integrated circuit design. He is a distinguished member of the Brazilian Millenium Group in Nanoelectronics and Microelectronics in 2006-2008. Dr. Petraglia served as an Associate Editor for the IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing in 2002–2003 Mariane Rembold Petraglia (M’97) received the B.Sc. degree in electronic engineering from the Federal University of Rio de Janeiro, Brazil, in 1985, and the M.Sc. and Ph.D. degrees in electrical engineering from the University of California, Santa Barbara, in 1988 and 1991, respectively. From 1992 to 1993, she was with the Department of Electrical Engineering, Catholic University of Rio de Janeiro, Brazil. Since 1993, she has been with the Department of Electronic Engineering and with the Program of Electrical Engineering, COPPE, at the Federal University of Rio de Janeiro, where she is presently an Associate Professor. From March 2001 to February 2002, she was a Visiting Researcher with the Adaptive Systems Laboratory, at the University of California, Los Angeles. Her research interests are in adaptive signal processing, multirate systems, and image processing. Dr. Petraglia is a member of Tau Beta Pi, and a distinguished member of the Brazilian Millenium Group in Nanoelectronics and Microelectronics in 2006–2008. She is serving as an Associate Editor for the IEEE Transactions on Signal Processing since Nov. 2004.     

Lone‐Pair‐Induced Covalency as the Cause of Temperature‐ and Field‐Induced Instabilities in Bismuth Sodium Titanate

Bismuth sodium titanate (BNT)‐derived materials have seen a flurry of research interest in recent years because of the existence of extended strain under applied electric fields, surpassing that of lead zirconate titanate (PZT), the most commonly used piezoelectric. The underlying physical and chemical mechanisms responsible for such extraordinary strain levels in BNT are still poorly understood, as is the nature of the successive phase transitions. A comprehensive explanation is proposed here, combining the short‐range chemical and structural sensitivity of in situ Raman spectroscopy (under an applied electric field and temperature) with macroscopic electrical measurements. The results presented clarify the causes for the extended strain, as well as the peculiar temperature‐dependent properties encountered in this system. The underlying cause is determined to be mediated by the complex‐like bonding of the octahedra at the center of the perovskite: a loss of hybridization of the 6s² bismuth lone pair interacting with the oxygen p‐orbitals occurs, which triggers both the field‐induced phase transition and the loss of macroscopic ferroelectric order at the depolarization temperature.     

Combustion Synthesized Zinc Oxide Electron‐Transport Layers for Efficient and Stable Perovskite Solar Cells

Perovskite solar cells (PSCs) have advanced rapidly with power conversion efficiencies (PCEs) now exceeding 22%. Due to the long diffusion lengths of charge carriers in the photoactive layer, a PSC device architecture comprising an electron‐ transporting layer (ETL) is essential to optimize charge flow and collection for maximum performance. Here, a novel approach is reported to low temperature, solution‐processed ZnO ETLs for PSCs using combustion synthesis. Due to the intrinsic passivation effects, high crystallinity, matched energy levels, ideal surface topography, and good chemical compatibility with the perovskite layer, this combustion‐derived ZnO enables PCEs approaching 17–20% for three types of perovskite materials systems with no need for ETL doping or surface functionalization.     

Pressure‐Tunable Ambipolar Conduction and Hysteresis in Thin Palladium Diselenide Field Effect Transistors

Few‐layer palladium diselenide (PdSe₂) field effect transistors are studied under external stimuli such as electrical and optical fields, electron irradiation, and gas pressure. The ambipolar conduction and hysteresis are observed in the transfer curves of the as‐exfoliated and unprotected PdSe₂ material. The ambipolar conduction and its hysteretic behavior in the air and pure nitrogen environments are tuned. The prevailing p‐type transport observed at atmospheric pressure is reversibly turned into a dominant n‐type conduction by reducing the pressure, which can simultaneously suppress the hysteresis. The pressure control can be exploited to symmetrize and stabilize the transfer characteristics of the device as required in high‐performance logic circuits. The transistors are affected by trap states with characteristic times in the order of minutes. The channel conductance, dramatically reduced by the electron irradiation during scanning electron microscope imaging, is restored after an annealing of several minutes at room temperature. The work paves the way toward the exploitation of PdSe₂ in electronic devices by providing an experiment‐based and deep understanding of charge transport in PdSe₂ transistors subjected to electrical stress and other external agents.     

Buffer losses vs. deadline violations for ABR traffic in an ATM switch: A computational approach

The B‐ISDN will carry a variety of traffic types: the Variable Bit Rate traffic (VBR), of which compressed video is an example, Continuous Bit Rate traffic (CBR), of which telemetry is an example, Data traffic, and Available Bit Rate traffic (ABR) that represents aggregate data traffic with very limited guarantees on quality. Of these, VBR and CBR have timing constraints and need synchronous bandwidth; data traffic is relatively delay insensitive. In this paper, we consider the VBR, Data and ABR traffic types and obtain the cumulative distribution function (cdf) of the queueing delay experienced by a burst of ABR traffic in the output buffer of an ATM switch. The cdf is used to trade off buffer loss probabilities against deadline violation probabilities through adjusting the buffer size and (delay) deadline values. Large buffers result in low losses but queueing delays can become excessive and cause a high level of deadline violations. Both losses and violations are detrimental and an operating point must be chosen to achieve a balance. In this paper we study the nature of the trade off. We develop a stochastic Petri net model assuming periodic burst arrivals for VBR and Poisson arrival processes for the Data and ABR traffic types at the burst level, and solve the model analytically (numerically) using a decomposition approach. This decomposition, along with the inherent decomposability of the tagged customer approach for obtaining the cdf opens up a possibility of carrying out fast computations using a parallel machine for selecting the operating point each time that a call is admitted. This revised version was published online in June 2006 with corrections to the Cover Date.