Implementation of ISO 14001:2004 (environmental management system standard) for reverse osmosis desalination plants for the first time in Iran

Implementation of ISO 14001:2004 (environmental management system) has been executed for reverse osmosis desalination plants for the first time in Iran at Noor Vijeh Company (N.V. Co), a water and wastewater firm based in Tehran. The scope of work was the activities and product of company's BWRO desalination plant in the city of Qom (3000 m³ per day) and SWRO desalination plant in Assaluyeh, Pars Special Economic and Energy Zone, Iran. The aims of this project were in line with company’s approach to sustainable development and its direction towards conducting environmental friendly activities and production characteristics.

Initially the famous PDCA (Plan, Do, Check, Act) was used to identify the aspects and evaluate their effects. The significant aspects of each plant affecting the environment are then identified and preventive control measures and reducing their probabilities of loss are anticipated. These cover the normal activities within each plant and those aspects arising from emergency conditions such as earthquakes, fire, etc.

Elements of this system are

• Environmental policy and its targets and programmes

• Practical methods for environmental management system processes

• Executive manuals for implementing special activities

• Tables and indexes for environmental aspects for each plant

• Organizational charts, positions, qualifications, and necessary trainings for the involved personnel.

Environmental aspects are evaluated through their interaction with and effects over, releases to water, emissions to air, land contamination, waste management, energy use, and use of natural resources and raw material.     

A 10-bit 50-MS/s redundant SAR ADC with split capacitive-array DAC

A new architecture for successive-approximation register analog-to-digital converters (SAR ADC) using generalized non-binary search algorithm is proposed to reduce the complexity and power consumption of the digital circuitry. The proposed architecture is based on the split capacitive-array DAC with a simple switching logic as compared to the conventional non-binary SAR ADC architecture. A 10-bit 50-MS/s SAR ADC is designed based on the proposed architecture in a 0.18 μm CMOS technology. Simulation results show that at a supply voltage of 1.2 V, the SAR ADC achieves a peak signal-to-noise-and-distortion ratio of 59.5 dB, and a power consumption of 1.3 mW, resulting in a figure of merit of 33 fJ/conversion-step.     

Novel Movable Typing for Personalized Vein-Chips in Large Scale: Recapitulate Patient-Specific Virchow's Triad and its Contribution to Cerebral Venous Sinus Thrombosis

The Vein-Chip recapitulates CVST Virchow's triad and enables systematic characterization of venous thrombogenesis with respect to fibrin formation and platelet aggregation. Distinct from the arterial setting, platelets universally adhere across the entire CVS Vein-Chip independent of stenotic geometry and flow disturbance. Intriguingly, fibrin propagates along with the flow direction, but exclusively deposits to the inner vessel wall. Upon inflammatory endothelial injury, fibrin deposition mirrors to the outer vessel wall, but still not in the lumen. Together, the Vein-Chip promises future applications for personalized thrombotic assessment and monitoring.