A Revised Criterion for the Portevin–Le Chatelier Effect Based on the Strain-Rate Sensitivity of the Work-Hardening Rate

An improved analysis is presented of the stability of plastic deformation under conditions where dynamic strain aging (DSA) occurs, which leads to instabilities known as the Portevin–Le Chatelier (PLC) effect. It is shown that PLC instabilities can occur for conditions that are not covered by the currently prevailing criterion presented by Estrin and Kubin (1991), which focuses on a negative strain rate sensitivity of the flow stress, caused by interactions of solutes with thermally activated glide of mobile dislocations. The current analysis recognizes that the strain-rate sensitivity of the flow stress consists of two contributions, one associated with glide of mobile dislocations and the second with work hardening, related to storage of immobile dislocations. In this paper, an instability criterion is proposed that takes into account the possibility of a negative strain-rate sensitivity of the work-hardening rate, which is caused by diffusion of solutes to immobile dislocations. The latter contribution leads to an extended instability criterion. This criterion also provides an explanation for the existence of a critical strain above which instabilities occur. In this article, previously published tensile test data are used to show that a negative strain-rate sensitivity of the work-hardening rate, which influences significantly the occurrence of the PLC effect, can indeed occur under DSA conditions.     

Electrochemical characteristics of semi conductive silicon anode for lithium polymer batteries

In this paper, the electrochemical characteristics of semi conductive silicon thin films (n-type and p-type silicon) anodes integrated with the solid polymer electrolyte for lithium polymer batteries were investigated. The charge/discharge cycling tests revealed that the phosphorus-doped n-type silicon electrode shows the most stable cyclic performance after the 40^th cycle and still maintains a reversible specific capacity of about 2,500 mAh/g. The enhanced electrochemical performance of the doped silicon anode was attributed to the enhancement of its electrical conductivity, which was further confirmed by impedance spectroscopy and surface analysis by XPS.     

An in-vitro method for prediction of the digestible crude protein content in pig feeds

An in-vitro method using commercially available enzymes for the prediction of the in-vivo digestible crude protein content was developed and tested on seven feedstuffs and 16 diets for pigs. Fat-extracted feed samples were consecutively incubated with pepsin at pH 1 and pancreatin at pH 6.8. From the nitrogen content of the feed sample and of the residue after incubation the in-vitro digestibility of the crude protein was calculated. Using the linear regression of in-vitro on in-vivo digestible crude protein of samples obtained in feeding trials, the in-vivo digestible crude protein content (DXP_p) in g kg^?1 dry matter could be predicted. For feedstuffs and diets the correlation was 0.99 and 0.95 and the residual standard deviation 17 and 6 g kg^?1 dry matter, respectively. In a similar procedure the nitrogen solubilised during incubation with enzymes was analysed. The regression value was similar to that of the original procedure. However, this procedure was abandoned because it was more laborious.     

Municipalities as a Driver for Wireless Broadband Access

Municipalities can form a driving force behind the deployment of new telecom infrastructure. While a telecom operator focuses on direct (financial) profits, a municipality is mainly interested in the social benefits for its inhabitants. In this paper, we evaluate a wireless municipality network from both a technical and an economic point of view. WiFi and WiMAX are considered as the most suited technologies for this purpose. A detailed techno-economic study has been performed including forecasting of the user adoption, dimensioning of the wireless network and modelling the related costs and revenues. The trade-off between installing a high number of relatively cheap WiFi access points, and a smaller number of more expensive WiMAX base stations for delivering full coverage is investigated in several scenarios.

Cost-Effective Triple-Mode Reconfigurable Pipeline FFT/IFFT/2-D DCT Processor

This investigation proposes a novel radix-4² algorithm with the low computational complexity of a radix-16 algorithm but the lower hardware requirement of a radix-4 algorithm. The proposed pipeline radix-4² single delay feedback path (R4²SDF) architecture adopts a multiplierless radix-4 butterfly structure, based on the specific linear mapping of common factor algorithm (CFA), to support both 256-point fast Fourier transform/inverse fast Fourier transform (FFT/IFFT) and 8times8 2D discrete cosine transform (DCT) modes following with the high efficient feedback shift registers architecture. The segment shift register (SSR) and overturn shift register (OSR) structure are adopted to minimize the register cost for the input re-ordering and post computation operations in the 8times8 2D DCT mode, respectively. Moreover, the retrenched constant multiplier and eight-folded complex multiplier structures are adopted to decrease the multiplier cost and the coefficient ROM size with the complex conjugate symmetry rule and subexpression elimination technology. To further decrease the chip cost, a finite wordlength analysis is provided to indicate that the proposed architecture only requires a 13-bit internal wordlength to achieve 40-dB signal-to-noise ratio (SNR) performance in 256-point FFT/IFFT modes and high digital video (DV) compression quality in 8 times 8 2D DCT mode. The comprehensive comparison results indicate that the proposed cost effective reconfigurable design has the smallest hardware requirement and largest hardware utilization among the tested architectures for the FFT/IFFT computation, and thus has the highest cost efficiency. The derivation and chip implementation results show that the proposed pipeline 256-point FFT/IFFT/2D DCT triple-mode chip consumes 22.37 mW at 100 MHz at 1.2-V supply voltage in TSMC 0.13-mum CMOS process, which is very appropriate for the RSoCs IP of next-generation handheld devices.     

Pure mode versus mixed mode interfacing between analog circuits

The concepts of transmission error and mismatch factor ^–1 are introduced to evaluate the effect of impedance mismatch on the accuracy of broadband signal transmission between two feedback amplifiers. It is shown that, in comparison with the error introduced by the feedback amplifiers, becomes negligible for pure V.M. (voltage mode) or C.M. (current mode) signal transmission; in the mixed mode, in which a V.M. output circuit feeds a C.M. input circuit, or vice versa, may become significant. Computer simulations show that the pure mode also yields reduced T.H.D., improved bandwidth and improved transient response. It is also shown that a particular combination between the kind of feedback and the active circuit to which it is applied, termed enhancing combination, further increases the accuracy of signal transmission.1. The notation (OL) relates to the open-loop value of the parameter involved.2. It can be shown that rule 2 does not apply to a low-noise preamplifier.     

Biasing a differential pair in low-voltage analog circuits: a systematic approach

This paper deals with a systematic approach to the common mode and the differential mode biasing of a differential transistor pair. Four different variants will be shown, two of these variants show practical importance; a practical circuit of one of these variants turns out to be the traditional long-tailed pair. This variant is mainly suited, if the input signal operates at voltage level, whereas another variant has great advantages if operation at current level occurs. Besides, the latter variant turns out to be very favorable in circuits operating with a single low supply voltage. Two practical circuits based on this variant are given.     

An asymptotic solution for the diffraction by a discontinuity in curvature coupled with surface diffraction

An extension is developed for the asymptotic theory of electromagnetic diffraction by a discontinuity in curvature on a smooth convex perfectly-conducting surface. It covers the case where the rays incident on and diffracted from the discontinuity are nearly tangent to the surface or are creeping rays, so that surface diffraction is involved. This extension is restricted to those diffracted rays lying on the same side of the discontinuity as the incident ray; this includes backscatter but excludes forward scattering.     

Performance analysis of linear MIMO equalizers for multitone DS/SS systems in multipath channels

In [11] the combination of multitone modulation with direct sequence spectrum spreading has been introduced. The performance of a correlation receiver has been evaluated for a multipath channel. In [12] the analysis has been extended to the presence of a multiple access interference. In the present paper we analyze the equalization problem of such a system for a single user scenario. In order to understand the potential of the system we first investigate the steady-state behavior of the MIMO equalizer for an MMSE design. The investigation is carried out for an equalizer following a receiver made of a bank of filters matched to both the symbol shape and the channel, which is a two-path channel. Assuming BPSK symbols an exact expression of the bit error probability before and after equalization is obtained in the form of an integral by means of the characteristic function method. Next adaptive LMS and RLS structures are proposed. The performance of the RLS algorithm is demonstrated.Part of this work has been presented at ICC '95, Seattle, June 1995.This author would like to thank the Belgian NSF for its financial support.This author is a Research assistant of FRIA.     

A power-efficient channel coder/decoder chip for GSM terminals

A compact power- and computing-delay-efficient channel codec chip for the Pan-European digital cellular radio (GSM) system is presented. This key component for the hand-portable mobile station, mainly implementing GSM Recommendation 5.03 on a full duplex basis, is accomplished through a dedicated architecture and application tailored memories. An important effort was made to increase the testability of the design; the sequentiality, the low pin count, and the presence of embedded macro functions implied the need for internal scan and BIST techniques. Full scan design and self-test facilities, supported by automatic test pattern generating software, resulted in time- and coverage-efficient testing. The chip is fabricated in a double-metal 1.2-μm CMOS technology, using a cell-based design approach incorporating memory and programmable array macro blocks. A full-rate speech channel block is decoded in less than 1.8 ms and typical average in-system power consumption does not exceed 10 mW