A current-reuse biomedical amplifier with a NEF < 1

Digital image authenticity is always an imperative question to tackle whenever a digital image is being assessed for its content. Using digital forensic algorithms, the image will be evaluated for various traces left from numerous categories of manipulations including, among others, copy–move operations. Later this is considered an essential block in most digital image forgeries. It results in changing the information incorporated in a scene, hiding information from an image, or emphasizing some parts of the image. In this paper we propose and investigate two main approaches that differ in the feature extraction process in order to detect copy–move traces. In the first method, we use two-dimensional discrete cosine transform. Whereas in the second method, the phase response of Gabor filter is being used. Instead of being applied on the image directly, the two methods are applied over the first, the second or the third principal component of the image after being divided into overlapping blocks. Combining these conditions results in six basic implementations that are investigated under three parameters that must be optimized: block dimension, contrast and similarity thresholds. Results from testing and validation process demonstrate that the highest performance, in terms of false accept rate, is obtained when using Gabor filter associated with the first principal component of the image outperforming a reference method we implemented as well.     

Do sewage treatment plant discharges substantially impair fish reproduction in polluted rivers?

Sewage treatment plants are frequently associated with the release of xenobiotics and, consequently, with alterations of the reproductive function induced by many of these substances in aquatic organisms. In order to assess the impacts of sewage treatment plant (STP) discharges in polluted rivers, two sentinel species (gudgeon Gobio gobio and stoneloach Barbatula barbatula) were caught during their reproductive cycle upstream and downstream two STPs (STP1--Goffontaine, STP2--Wegnez). Gonadosomatic index, histological (testicular and ovarian stages, atretic follicles, intersexuality) and endocrine (sex steroids, aromatase activity, alkali-labile phosphorus) parameters were assayed. In brief, the results revealed no systematic significant differences (p<0.05) between upstream and downstream sites, whatever the STP, species or sampling period. However, stoneloach females displayed some signs of reproductive impairment and endocrine disruption downstream STP1 (reduced GSI, oocyte diameter and ALP concentrations, increased proportion of atretic follicles) and STP2 (changes in gonadal aromatase activity and plasma levels of 11-KT and T). Few significant changes were observed for gudgeon males and females while there were no significant differences between upstream and downstream sites for stoneloach males. Moreover, plasma E(2) concentrations recorded in gudgeon males sampled in all sites were as high as in females and this was confirmed by high ALP levels. Besides, spermatogenesis of gudgeon males was delayed in STP1 upstream and downstream sites compared to the corresponding sites in STP2. These observations for gudgeon males do not seem related to STP discharge but to a probable estrogenicity of the river. Therefore, as shown by the results, stoneloach seemed more sensitive than gudgeon to STP discharges. In the present study, sewage treatment plant discharges do not substantially impair fish reproduction. In this respect, caution is required when generalising negative impacts of STP discharges.     

CMOS level shifters from 0 to 18 V output

A design methodology for level shifters voltage translators, where the output voltage ranges from 0 to 18 V, and the input voltage ranges from 2 to 5.5 V in a 0.6 µm CMOS-HV technology, is presented. This family of circuits have a special interest in the case of implantable medical devices where is common to handle previously unknown voltages either positive or negative, above or below the control logic supply V_DD. Two application examples are presented: a composite switch to control negative stimuli voltage pulses, and a multi-channel programmable charge-pump voltage multiplier, aimed at charging the output capacitors of an IMD.

     

Formation and Etching of the Insulating Sr-Rich V5+ Phase at the Metallic SrVO3 Surface Revealed by Operando XAS Spectroscopy Characterizations

In the search of low cost and more efficient electronic devices, here the properties of SrVO₃ transparent conductor oxide (TCO) thin film are investigated, both visible-range optically transparent and highly conductive, it stands as a promising candidate to substitute the standard indium-tin-oxide (ITO) in applications. Its surface stability under water (both liquid and vapor) and other gaseous atmospheres is especially addressed. Through the use of spectroscopy characterizations, X-ray photoemission and operando X-ray absorption measurements, the formation of a thin Sr-rich V⁵⁺ layer located at the surface of the polycrystalline SrVO₃ film with aging is observed, and for the first time how it can be removed from the surface by solvating in water atmosphere. The surface recovery is associated to an etching process, here spectroscopically characterized in operando conditions, allowing to follow the stoichiometric modification under reaction. Once exposed in oxygen atmosphere, the Sr-rich V⁵⁺ layer forms again. The findings improve the understanding of aging effects in perovskite oxides, allowing for the development of functionalized films in which it is possible to control or to avoid an insulating surface layer. This constitutes an important step towards the large-scale use of V-based TCOs, with possible implementations in oxide-based electronics.     

Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test

This paper presents the results of resistive-open defect insertion in different locations of Infineon 0.13 m embedded-SRAM with the main purpose of verifying the presence of dynamic faults. This study is based on the injection of resistive defects as their presence in VDSM technologies is more and more frequent. Electrical simulations have been performed to evaluate the effects of those defects in terms of detected functional faults. Read destructive, deceptive read destructive and dynamic read destructive faults have been reproduced and accurately characterized. The dependence of the fault detection has been put in relation with memory operating conditions, resistance value and clock cycle, and the importance of at speed testing for dynamic fault models has been pointed out. Finally resistive Address Decoder Open Faults (ADOF) have been simulated and the conditions that maximize the fault detection have been discussed as well as the resulting implications for memory test.This work has been partially funded by the French government under the framework of the MEDEA + A503 ASSOCIATE European program.A paper based on this work was presented at the Eighth IEEE European Test Workshop, Maastricht, The Netherlands, May 2003.Simone Borri received the M.Sc. Degree (summa cum laude) in Electronics Engineering from the University of Pisa (Italy) in 1995. In 1997 he joined STMicroelectronics as a digital designer in the DSP development group of S.S.D. (formerly Parthus, now Ceva), Dublin, Ireland. From 1998 to 2000 he was with ST Microelectronics, Milan, Italy as ASIC DSP designer in the Car Communication business unit. Since 2000 he is with Infineon Technologies, Sophia-Antipolis, France as Staff design engineer in the embedded-SRAM design group. He has recently joined the Secure Mobile System Business Unit. His current interests include BIST, DFT techniques and SoC verification. Simone is an IEEE member since 1995.Magali Hage-Hassan was born near Lyon (France) in 1979. She received a Master of Science degree of Microelectronics and Automatics from the Institute of Engineering Sciences of Montpellier in 2003. She is currently working for Infineon in the memory library department in Sophia-Antipolis. She participated to the European research project MEDEA associate. Hage-Hassans interest include memory test.Luigi Dilillo was born in Barletta (Italy) in 1974. At this moment he is doing his last year of Ph.D. in the Microelectronics Department of the Laboratory of Informatics, Robotics and Microelectronics of Montpellier (LIRMM) in France. He received his degree in Electrical Engineering in 2001, at Politecnico di Torino (Italy). His researches include MEMS and digital circuits. At this moment he is working on delay-fault testing, and memory testing.Patrick Girard is presently Researcher at CNRS (French National Center for Scientific Research), and works in the Microelectronics Department of the LIRMM (Laboratory of Informatics, Robotics and Microelectronics of Montpellier—France). His research interests include the various aspects of digital testing, with special emphasis on DfT, logic BIST, delay fault testing and diagnosis, low power testing and memory testing. He has authored and co-authored 1 book and more than 100 papers on these fields. He has managed several European research projects and industrial research contracts. He is Editor-in-Chief of JOLPE—Journal of Low Power Electronics, and Associate Editor of JEC—Journal of Embedded Computing. He will serve as Program vice-Chair for the International Conference on Embedded And Ubiquitous Computing in 2005 and as Program Chair for the IEEE International Workshop on Electronic Design, Test & Applications in 2006. He is also topic chair of two European conferences (DATE and ETS) and is member of the program committee of several other international conferences. Patrick GIRARD obtained the Ph.D. degree in microelectronics from the University of Montpellier in 1992 and the Habilitation à Diriger des Recherches degree from the University of Montpellier in 2003.Serge Pravossoudovitch was born in 1957. He is currently professor in the electrical and computer engineering department of the University of Montpellier and his research activities are performed at LIRMM (Laboratoire dInformatique, de Robotique et de Microélectronique de Montpellier). He got the Ph.D. degree in electrical engineering in 1983 for his work on symbolic layout for IC design. Since 1984, he is working in the testing domain. He obtained the doctorat détat degree in 1987 for his work on switch level automatic test pattern generation. He is presently interested in memory testing, delay fault testing, design for testability and power consumption optimization. He has authored and co-authored numerous papers on these fields, and has supervised several Ph.D. dissertations. He has also participated to several European projects (Microelectronic regulation, Esprit, Medea).Arnaud Virazel was born in Montpellier (France) in 1974. He is presently assistant professor at the university of Montpellier, and works with the LIRMM (Laboratoire dInformatique, de Robotique et de Microélectronique de Montpellier). He received the B.Sc. (1995) and the M.Sc. (1997) degrees in Electrical Engineering and the Ph.D. (2001) degree in Microelectronics, all from the University of Montpellier/LIRMM. A. Virazels interests include delay testing, memory testing and power optimization during test.     

Synthesis of 6‐Substituted 7‐Bomoazabicyclo[2.2.1]heptanes via Nucleophilic Addition to 3‐Bromo‐1‐azoniatricyclo[2.2.1.0]‐heptane Bromide

We describe herein an efficient method for the preparation of a functionalised bicyclic framework (6‐substituted 7‐bromo‐aza‐bicyclo[2.2.1]heptane) through the selective opening of the aziridium 2 with organocuprates in up to 90% yield. These interesting chiral building blocks were then utilised as novel ligands in the rearrangement of epoxides to afford chiral allylic alcohols.