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21.
In this work, we report the preparation of phospho-silicate-glass (PSG) films using RF magnetron sputtering process and its application as a sacrificial layer in surface micromachining technology. For this purpose, a 76 mm diameter target of phosphorus-doped silicon dioxide was prepared by conventional solid-state reaction route using P2O5 and SiO2 powders. The PSG films were deposited in a RF (13.56 MHz) magnetron sputtering system at 200-300 W RF power, 10-20 mTorr pressure and 45 mm target-to-substrate spacing without external substrate heating. To confirm the presence of phosphorus in the deposited films, hot-probe test and sheet resistance measurements were performed on silicon wafers following deposition of PSG film and a drive-in step. As a final confirmatory test, a p-n diode was fabricated in a p-type Si wafer using the deposited film as a source of phosphorus diffusion. The phosphorus concentration in the target and the deposited film were analyzed using energy dispersive X-rays (EDAX) tool. The etch rate of the PSG film in buffered HF was measured to be about 30 times higher as compared to that of thermally grown SiO2 films. The application of RF sputtered PSG film as sacrificial layer in surface micromachining technology has been explored. To demonstrate the compatibility with MEMS process, micro-cantilevers and micro-bridges of silicon nitride were fabricated using RF sputtered PSG as a sacrificial layer in surface micromachining. It is envisaged that the lower deposition temperature in RF sputtering (<150 °C) compared to CVD process for PSG film preparation is advantageous, particularly for making MEMS on temperature sensitive substrates.  相似文献   
22.
In this paper, the authors derive symbol error probability (SEP) expressions for coherent M‐ary frequency shift keying (MFSK) modulation schemes in multipath fading channels. The multipath or small‐scale fading process is assumed to be slow and frequency non‐selective. In addition, the channel is also subjected to the usual degradation caused by the additive white Gaussian noise (AWGN). Different small‐scale fading statistics such as Rayleigh, Rician (Nakagami‐n), Hoyt (Nakagami‐q), and Nakagami‐m have been considered to portray diverse wireless environments. Further, to mitigate fading effects through space diversity, the receiver front‐end is assumed to be equipped with multiple antennas. Independent and identically distributed (IID) as well as uncorrelated signal replicas received through all these antennas are combined with a linear combiner before successive demodulation. As the detection is coherent in nature and thus involves phase estimation, optimum phase‐coherent combining algorithms, such as predetection maximal ratio combining (MRC), may be used without any added complexity to the receiver. In the current text, utilizing the alternate expressions for integer powers (1≤n≤4) of Gaussian Q function, SEP values of coherent MFSK are obtained through moment generating function (MGF) approach for all the fading models (with or without MRC diversity) described above. The derived end expressions are composed of finite range integrals, which can be numerically computed with ease, dispenses with the need of individual expressions for different M, and gives exact values up to M=5. When the constellation size becomes bigger (M≥6), the same SEP expressions provide a quite realistic approximation, much tighter than the bounds found in previous literatures. Error probabilities are graphically displayed for each fading model with different values of constellation size M, diversity order L, and for corresponding fading parameters (K, q, or m). To validate the proposed approximation method extensive Monte‐Carlo simulations were also performed, which show a close match with the analytical results deduced in the paper. Both these theoretical and simulation results offer valuable insight to assess the efficacy of relatively less studied coherent MFSK in the context of the optimum modulation choice in wireless communication. Copyright © 2010 John Wiley & Sons, Ltd.  相似文献   
23.
Arsenic-doped mid-wavelength infrared HgCdTe photodiodes   总被引:1,自引:0,他引:1  
The recently developed Te-rich, liquid-phase-epitaxy growth technology for low arsenic-doped mid-wavelength infrared (MWIR) HgCdTe with p-type doping concentrations <1015 cm−3 has enabled the fabrication of n+/p photodiodes using the damage associated with a boron ion implantation. The diode properties are presented and compared to similar diodes fabricated in p-HgCdTe doped with Group IBs. The attraction of the arsenic-doped diode technology is associated with the fact that the arsenic resides on the Te sublattice and is immune to the Hg interstitial fluxes that are present in the diode-formation process. This leads to minimal diode spread, limited primarily to the n+ region and, hence, a potential for use in really high-density infrared focal planes. At the same time, the Hg interstitials generated in the diode-formation process should purge the photodiode volume of fast diffusing species, resulting in a high-quality, diode-depletion region devoid of many Shockley-Read recombination centers. These aspects of diode formation in this material are discussed.  相似文献   
24.
This paper presents abstract layout techniques for a variety of field-programmable gate array switch block architectures. For subset switch blocks of small size, we find the optimal implementations using a simple metric. We also develop a tractable heuristic that returns the optimal results for small switch blocks and good results for large switch blocks. We show how it is possible to transform universal switch blocks into a subset architecture by using the decomposition property of universal switch blocks. This allows universal switch blocks to exploit the same layout methodologies as presented for subset architectures.  相似文献   
25.
This paper presents a self-generating square/triangular wave generator using only the CMOS Operational Transconductance Amplifiers (OTAs) and a grounded capacitor. The output frequency and amplitude of the proposed circuit can be independently and electronically adjusted. The proposed circuit validates its advantage by consuming less amount of power, which is about 71.3 µW. The theoretical aspects are authentically showcased using the PSPICE simulation results. The performance of the proposed circuit is also verified through pre layout and post layout simulation results using the 90 nm GPDK CMOS parameters. A prototype of this circuit has been made using commercially available IC CA3080 for experimental verification. Experimentation also gives the similar output as per the theoretical proposition. The designed circuit is also made applicable to perform pulse width modulation (PWM).  相似文献   
26.
In this paper, formulae to determine the lowest order and other higher order spurious frequencies that coincide with desired output signal frequencies of mixers have been derived. The proposed formulae give general expressions that are suitable for any order of heterodyne mixing. The formulae have been verified using a suitable example and compared with the simulation results obtained through the radio frequency simulation software of Advanced Design System. The formulae directly reveal the order of the troublesome spurious frequencies that the designers would encounter in heterodyne systems. In comparison with these direct formulae, the results of existing spurious analysis software are based on the maximum order of simulation carried out. Based on these simulations, the coinciding spurious components have to be manually sorted out. Proposed formulae are quick tools used by the microwave system and circuit designers for choosing and finalizing heterodyne frequencies in their designs without the need for any simulations.  相似文献   
27.
Simulation is an important tool to study and analyze sensor networks. Prior work in sensor network simulation focuses on homogeneous devices. In this paper, we present a system that performs scalable and accurate simulation of a network of heterogeneous sensor devices, including both Stargate intermediate level devices and mote devices. We study accuracy, performance, and scalability of our system. The results show that we can achieve accurate functional behavior for both standalone Stargate simulation and ensemble simulation of a Stargate and motes. For motes, we have less than 4.06% cycle count error for all benchmarks and for Stargate, we have less than 10% error for most benchmarks, and less than 12.5% error for all benchmarks. We also achieve less than 3.6% error for all benchmarks when simulating an ensemble of Stargate and motes. Our system is also more scalable than prior work. We can simulate 160 sensor nodes in real time speed and 2,048 sensor nodes with ten times slowdown on a 16-node cluster.
Chandra KrintzEmail:
  相似文献   
28.
In this work, quaternary chalcogenide Cu2ZnSnSe4 (CZTSe) was synthesized using a mechanochemical ball milling process and its thermoelectric properties were studied by electrical resistivity, Seebeck coefficient, and thermal conductivity measurements. The synthesis process comprises three steps viz., wet ball milling of the elemental precursors, vacuum annealing, and densification by hot pressing. The purpose of this is to evaluate the feasibility of introducing wet milling in place of vacuum melting in solid state synthesis for the reaction of starting elements. We report the structural characterization and thermoelectric studies conducted on samples that were milled at 300 rpm and 500 rpm. X-ray diffraction (XRD) analysis showed the existence of multiple phases in the as-milled samples, indicating the requirement for heat treatment. Therefore, the ball milled powders were cold pressed and vacuum annealed to eliminate the secondary phases. Annealed samples were hot pressed and made into dense pellets for further investigations. In addition to XRD, energy dispersive spectroscopy (EDS) studies were performed on hot pressed samples to study the composition. XRD and EDS studies confirm CZTSe phase formation along with ZnSe secondary phase. Electrical resistivity and Seebeck coefficient measurements were done on the hot pressed samples in the temperature range 340–670 K to understand the thermoelectric behaviour. Thermal conductivity was calculated from the specific heat capacity and thermal diffusivity values. The thermoelectric figure of merit zT values for samples milled at 300 rpm and 500 rpm are ~0.15 and ~0.16, respectively, at 630 K, which is in good agreement with the values reported for solid state synthesized compounds.  相似文献   
29.
We report on four-point probe measurements on SiC wafers as such measurements give erratic data. Current-voltage measurements on n-type SiC wafers doped to 3 × 1018 cm−3 are non-linear and single probe I-V measurements are symmetrical for positive and negative voltages. For comparison, similar measurements of p-type Si doped to 5 × 1014 cm−3 gave linear I-V, well-defined sheet resistance and the single probe I-V curves were asymmetrical indicating typical Schottky diode behavior. We believe that the reason for the non-linearity in four-point probe measurements on SiC is the high contact resistance. Calculations predict the contact resistance of SiC to be approximately 1012 Ω which is of the order of the input resistance of the voltmeter in our four-point probe measurements. There was almost no change in two-probe I-V curves when the spacing between the probes was changed from 1 mm to 2 cm, further supporting the idea that the I-V characteristics are dominated by the contact resistance.  相似文献   
30.
Evolutionary computational techniques have been employed judiciously in various signal processing applications of late. In this paper, such an attempt has been made to design a low-pass linear-phase multiplier-less finite duration impulse response (FIR) filter using differential evolution (DE) algorithm. This particular evolutionary optimization technique has been explored to search the impulse response coefficients of the FIR filter in the form of sum of power of two (SPT) in order to avoid the multipliers during design process. The performance of the designed low-pass filter has been studied thoroughly in terms of its frequency characteristics and primitive requirement of fundamental hardware blocks. The superiority of our design has been ascertained over a number of existing techniques by various means. Finally, the proposed filter of different lengths has been implemented on a field programmable gate array (FPGA) chip for evaluating the competency of this work. The percentage improvement in hardware complexity produced by our design has also been computed and clearly listed in this paper for convenience.  相似文献   
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