Modeling frequency dependence of GaAs MESFET characteristics

We present a new method of modeling the output conductance dispersion of GaAs MESFET's. High frequency model parameters are extracted and then used to model high frequency output conductance over a wide range of bias conditions. The model is then used to simulate and analyze the effect of output conductance dispersion on the performance of DCFL and SCFL logic gates. Whereas the DCFL performance is not significantly affected by the high frequency effects, the noise margin of SCFL decreases by almost a factor of 30% above 100 kHz, with an associated decrease in the voltage swing and gate delay     

Experimental study of the thermal conductivity of heat insulation materials based on expanded vermiculite

Results are presented for experimental studies of the thermal conductivity of expanded vermiculite. Tests are performed in an experimental test unit by a steady-state heat flux. Thermal studies are carried out in the range 300–1100 K. It is shown that thermal conductivity increases uniformly with an increase in temperature. The most probable reason for an increase in thermal conductivity is the effect of heat radiation. Results are provided for an approximate second power polynomial. __________ Translated from Novye Ogneupory, No. 11, pp. 41–43, November 2007.     

Evaluation of the N- and La-induced defects in the high-κ gate stack using low frequency noise characterization

Low frequency noise (LFN) characterization was performed on the HfSiON gate stacks fabricated with the SiON interfacial layers (ILs) and a La cap layer. The LFN data identified N and La related defects located in the IL/HK region.     

Self-heating and kink effects in a-Si:H thin film transistors

We describe a new physics based, analytical DC model accounting for short channel effects for hydrogenated amorphous silicon (a-Si:H) thin film transistors (TFT's). This model is based on the long channel device model. Two important short-channel phenomena, self-heating and kink effects, are analyzed in detail. For the self-heating effect, a thermal kinetic analysis is carried out and a physical model and an equivalent circuit are used to estimate the thermal resistance of the device. In deriving the analytical model for self-heating effect, a first order approximation and self-consistency are used to give an iteration-free model accurate for a temperature rise of up to 100°C. In the modeling of the kink effects, a semi-empirical approach is used based on the physics involved. The combined model accurately reproduces the DC characteristics of a-Si:H TFT's with a gate length of the 4 μm. Predictions for a-Si:H TFT's scaled down to 1 μm are also provided. The model is suitable for use in device and circuit simulators     

New continuous heterostructure field-effect-transistor model andunified parameter extraction technique

A continuous model for heterostructure field-effect transistors (HFETs) suitable for circuit simulation and device characterization is proposed. The model is based on the analytical solution of a two-dimensional Poisson equation in the saturation region. The HFET saturation current and saturation voltage have been experimentally determined by differentiating the output characteristics in a unified and unambiguous way. The results are used for the systematic extraction of device and process parameters. The deduced values agree well with other independent measurements. The results of experimental studies of HFETs with nominal gate lengths of 1, 1.4, 2, and 5 μm are reported. The models and techniques presented here are successfully applied to all these devices. A large short-channel effect is observed for the 1-μm-gate HFET. The gate length dependences of the device parameters determined by the method reveal that the effective gate length in the self-aligned structures is approximately 0.25 μm shorter than the nominal gate length     

Steady-state electron transport in the III–V nitride semiconductors: A sensitivity analysis

We studied the sensitivity of the steady-state electron transport in GaN to variations in the important material parameters related to the band structure. We found (a) that an increase in the lowest conduction-band-valley effective mass leads to a lowering and broadening of the peak in the velocity-field characteristic, as well as to an increase in the field at which the peak occurs; (b) that increases in the upper conduction-band-valley effective masses dramatically decrease the saturation drift velocity, with very little other effect; (c) that increased nonparabolicity of the lowest conduction-band valley leads to a broadening and shifting to higher electric fields of the peak in the velocity-field characteristic; (d) that increases in the intervalley energy separation lead to moderate increases in the peak drift velocity; and (e) that increases in the degeneracy of the upper conduction-band valleys leads to a moderate decrease in the saturation drift velocity.     

Effect of p-i-p+ buffer on characteristics of n-channelheterostructure field-effect transistors

The carrier concentration in heterostructure FETs (HFETs) with a p-i-p⁺ buffer is presented as a function of the gate bias, obtained by self-consistent one-dimensional calculation of 2-D electron density, subband levels, and electrostatic potential. These results quantify certain limitations on the range of geometrical and doping parameters and make it possible to optimize the HFET design and to compare modulation doped FET (MODFET) and doped channel HFET (DCHFET) structures. Monte Carlo simulations demonstrate that this p-i-p⁺ buffer drastically reduces the short-channel effects     

Analysis of bias stress on unpassivated hydrogenated amorphoussilicon thin-film transistors

Both the subthreshold slope and the threshold voltage in inverted-staggered amorphous silicon thin-film transistors (a-Si:H TFTs) are vulnerable to metastable changes in the density of states (DOS) due to Fermi level displacement. In previous work, we have used passivated and unpassivated TFTs to distinguish between the effects of bulk states and interface states at the top passivating nitride interface. Here we report the results of experimental measurements and two-dimensional (2-D) simulations on unpassivated TFTs. Since there are no top interface states, all the observed changes are due solely to the bulk DOS. The subthreshold current activation energies in a-Si:H TFTs are compared for n-channel nonpassivated TFTs before and after bias stress. The experimental results agree well with the 2-D simulations, confirming that the dependence of subthreshold current activation energy on gate bias reveals the distribution of the DOS in energy but cannot resolve the magnitude of features in the DOS. This type of analysis is not accurate for TFTs with a top passivating nitride, since the activation energies in such devices are affected by the interfere states     

Unified quasi-static MOSFET capacitance model

An accurate calculation of MOSFET capacitance-voltage (C V) characteristics has to account for the bulk charge which is affected by nonuniform doping profiles and short-channel effects. In an approach based on the unified charge control model (UCCM), the voltage dependencies of the bulk charge are related to the standard parameters of the body plots which are routinely measured during MOSFET characterization. The results of the C-V calculations based on this model are in good agreement with experimental data and calculations based on the standard BSIM model. Compared to the BSIM simulations, the present model more accurately describes capacitances related to the bulk charge and the device subthreshold behavior, and it is suitable for incorporation into circuit simulators     

Threshold voltage modeling and the subthreshold regime of operationof short-channel MOSFETs

An analytical model for the subthreshold regime of operation of short-channel MOSFETs is presented, and expressions for the threshold-voltage shift associated with the drain-induced barrier lowering (DIBL) caused by the application of a drain bias are developed. The amount of drain-bias-induced depletion charge in the channel is estimated, and an expression for the distribution of this charge along the channel is developed. From this distribution, it is possible to find the lowering of the potential barrier between the source and the channel, and the corresponding threshold-voltage shift. The results are compared with experimental data for deep-submicrometer NMOS devices. Expressions for the subthreshold current and for a generalized unified charge control model (UCCM) for short-channel MOSFETs are presented. The theory is applicable to deep-submicrometer devices with gate lengths larger than 0.1 μm. The model is suitable for implementation in circuit simulators