Signal integrity analysis on a microstrip ultra-wideband coupled-line coupler

In this paper, a compact, single-section, Ultra-wideband (UWB) coupled-line coupler designed using concentric loop in the signal plane and defect in the ground plane is presented. Bandwidth enhancement is achieved with low coupling at the X-band satellite downlink range to improve the signal strength for defence applications. Return loss greater than 15 dB and isolation greater than 20 dB is achieved over the entire UWB band. The prototype is fabricated and tested to validate the simulation results. Further to detect the quality of the output signal, signal integrity analysis is performed and metrics such as error vector magnitude (EVM), magnitude and phase error, eye pattern, constellation plots and signal to noise ratio are presented for the proposed UWB coupled-line coupler.     

Fuzzy-Based Cluster Head Amendment (FCHA) Approach to Prolong the Lifetime of Sensor Networks

Wireless Personal Communications - Wireless sensor networks (WSN) consist of large number of sensor nodes that work collaboratively. Sensors segregate groups with similar traits and get arranged in...     

A unified approach to the real-time implementation ofmicroprocessor-based PWM waveforms

A method for real-time implementation of any two-level three-phase pulse-width-modulator (PWM) invertor waveform is discussed. The hardware and software of the scheme are built around the 16 b 8086 microprocessor and its peripherals, with a few additional digital ICs. The suggested scheme realizes the PWM waveforms without harmonic distortion. The implementation procedure is a universal one and it generates in real time any two-level three-phase PWM waveform with the chosen hardware structure. There is no need for hardware alteration for realization of different types of PWM waveforms     

A New and Faster Gaussian Elimination Based Fault Tolerant Systolic Linear System Solver

This paper presents a new systolic algorithm for thecompletesolution of a system ofNlinear equations in (N²/2 +O(N)) time steps using 2Nprocessing elements (PEs). It is based on a variant of the Gaussian elimination (GE) algorithm called the successive GE and is faster than any existing GE based algorithm usingO(N) PEs. We also suggest two fault tolerant schemes that tolerate up toNPE failures. The first scheme is a time redundancy based approach with no hardware overhead and 100% time overhead. This scheme can tolerate up toNPE failures. The second scheme is based on algorithm based fault tolerance (ABFT) and usesNextra PEs to tolerate up toN− 1 PE failures with very little time overhead. The number of errors that can be detected/corrected in both schemes is more than that in any existing fault tolerant systolic array.     

Lie group analysis of radiation natural convection heat transfer past an inclined porous surface

Natural convection heat transfer fluid flow past an inclined plate embedded in a fluid-saturated porous medium is investigated by Lie group analysis. The governing partial differential equations are reduced to a system of ordinary differential equations by the scaling symmetries. From numerical results, it is found that the thermal and momentum boundary layer thicknesses are increased as the radiation parameter is increased. Also, it is observed that the velocity is increased and the temperature is decreased for increasing the buoyancy parameter and the porosity parameter.     

Scheduling and resources allocation in network traffic using multiobjective,multiuser joint traffic engineering

Wireless Networks - Reciprocal optimality is a desirable characteristic from the end user perspective, for both Best Effort and Quality of Service (QoS) datagrams delivery within a network. A...     

Reversed signal propagation BDD based low‐power pass‐transistor logic synthesis

Binary decision diagrams (BDDs) are the most frequently used data structure for the representation and manipulation of Boolean functions in the area of Very Large Scale Integration (VLSI) CAD. In this paper, we propose the reversed‐signal‐propagation (RSP) BDD‐based low‐power pass‐transistor logic (PTL) synthesis. In RSP BDD, the signal flow direction is opposite to that of the forward BDD. So the power supply is taken as a root node and the terminal nodes 0 and 1 represent the function in its normal and complement form. We propose an efficient way to construct the multi‐output function RSP BDD and its PTL realization. Simulation results of the proposed method give lower power consumption and high performance as a result of reduced switching activity than the existing techniques. The power improvement is about 70–80% compared to the existing techniques. © 2013 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

An accurate and economical approach for induction motor field efficiency estimation using bacterial foraging algorithm

As the demand of electrical energy increases, it is vital to replace inefficient motors with new energy efficient ones. The first step towards achieving this goal is to estimate the existing motors efficiencies accurately to determine how much energy saving will be achieved by using energy efficient motors. This paper proposes an economical and accurate approach for motor field efficiency estimation using bacterial foraging algorithm. The approach relies on the measurement of the stator current, stator voltage, input power, stator resistance and rotor speed of the motor without conducting no-load and locked-rotor tests. The BF algorithm is used to determine the equivalent circuit parameters of the motor. The efficiency is then estimated using these parameters. The advantages of the proposed method over the existing methods are simple procedure, efficiency can be estimated accurately without conducting any invasive tests and inexpensive. The approach has been tested on a 5 HP motor and the results are compared with particle swarm optimization method, immune algorithm method, torque gauge method, equivalent circuit method, slip method, current method and segregated loss method. The results demonstrate that the proposed approach can accurately estimate the field efficiency of motor. Accordingly, it is suitable for conducting energy audits and management of the motor.     

Electrical characteristics of ZrN metallised metal-oxide-semiconductor and metal-insulator-metal devices

The electrical properties of DC reactive sputtered zirconium-nitride metallized metal-oxide-semiconductor (MOS) and metal-insulator-metal (MIM) devices on TiO₂/p-Si and TiO₂/ZrN films were studied using capacitance-voltage (C-V) and current-voltage (I-V) measurements at room temperature. Capacitances of the ZrN/TiO₂/p-Si MOS device were measured in accumulation mode and inversion mode, from which flat band capacitance was found to be 2.86pF, which corresponds to flat band voltage of −1.7 V. Fixed oxide charged density and interface state density was found to be 1.63× 10¹⁰ cm⁻² and 6.3× 10¹¹ cm⁻² eV⁻¹. I-V characteristics revealed that the leakage current density was of 0.5 mA/cm² in accumulation mode and 2 mA/cm² in inversion mode at a field of 0.12 MV/cm, respectively. Dielectric breakdown of ZrN/TiO₂/p-Si device was found to be 0.12 MV/cm in accumulation mode. Based on the C-V and I-V characteristics, the ZrN/TiO₂/ZrN structure showed no variation in the capacitance value as the bias voltage was changed.