High Brightness GaN-Based Light-Emitting Diodes

This paper reviews our recent progress of GaN-based high brightness light-emitting diodes (LEDs). Firstly, by adopting chemical wet etching patterned sapphire substrates in GaN-based LEDs, not only could increase the extraction quantum efficiency, but also improve the internal quantum efficiency. Secondly, we present a high light-extraction 465-nm GaN-based vertical light-emitting diode structure with double diffuse surfaces. The external quantum efficiency was demonstrated to be about 40%. The high performance LED was achieved mainly due to the strong guided-light scattering efficiency while employing double diffuse surfaces     

Run-by-Run Process Control of Metal Sputter Deposition: Combining Time Series and Extended Kalman Filter

By the time series model, this paper constructed the disturbance model for the aluminum sputter deposition process and derived the extending Kalman filter (EKF) controller based on this new disturbance model. Experimental results reveal that ARI(3,1) model appropriately characterizes the dynamic behavior of the disturbance for the processes. The EKF controller which includes information of process noise and measurement noise is able to regulate the model coefficients automatically as the target is replaced or degrades. In this paper, the d-EWMA controller, time-varying d-EWMA controller, age-based d-EWMA controller, and EKF controller have been applied to aluminum sputter deposition processes for predicting deposition rates and comparing their performances. The application of the EKF controller here is proven to improve the estimating accuracy of the aluminum sputter deposition process significantly, regardless of whether the deposition rates are measured at each run or not.     

Single nucleotide polymorphism data analysis - State-of-the-art review on this emerging field from a signal processing viewpoint

The basic structural units of the genome are nucleotides. A single nucleotide polymorphism (SNP) is a mutation at a single nucleotide position. This paper discusses several major problems in SNP data analysis and review some existing solutions in this work. Generally speaking, a rich set of SNP analysis problems are cast in the signal processing framework. Our objective is to offer a state-of-the art review on this topic from a signal processing viewpoint so that researchers in the signal processing field can grasp the important domain knowledge to overcome the barrier between the two fields     

Characterization and Properties of Nickel Aluminide Nanocrystals in an Alumina Layer for Nonvolatile Memory Applications

Intermetallic nanocrystal memory devices with nickel aluminide nanocrystals in the electron-trapping layer and an alumina layer as the blocking layer were prepared on the surface of oxidized silicon substrates by sputter-coating of Ni and Al₂O₃ in sequence, followed by an annealing procedure. Several aluminide nanocrystal memory devices are reported. The effect of annealing at 900°C on the memory properties was investigated. Intermetallic nanocrystals were identified by high-resolution transmission electron microscopy and x-ray photoelectron spectroscopy as Ni₂Al₃ with sizes of 15–20 nm. The results showed that a sixfold increase (0.37 V to 2.34 V) in the memory window could be achieved after annealing for the optimal time of 3 min.     

28 nm低功耗工艺SRAM失效分析

在28 nm低功耗工艺平台开发过程中,对1.26 V测试条件下出现的SRAM双比特失效问题进行了电性能失效模式分析及物性平面和物性断面分析.指出失效比特右侧位线接触孔底部空洞为SRAM制程上的缺陷所导致.并通过元素成分分析确定接触孔底部钨(W)的缺失,接触孔底部外围粘结阻挡层的氮化钛(TiN)填充完整.结合SRAM写操作的原理从电阻分压的机理上解释了较高压下双比特失效,1.05 V常压下单比特不稳定失效,0.84 V低电压下失效比特却通过测试的原因.1.26 V电压下容易发生的双比特失效是一种很特殊的SRAM失效,其分析过程及结论在集成电路制造行业尤其是对先进工艺制程研发过程具有较好的参考价值.     

H.264/SVC mode decision based on optimal stopping theory

Fast mode decision algorithms have been widely used in the video encoder implementation to reduce encoding complexity yet without much sacrifice in the coding performance. Optimal stopping theory, which addresses early termination for a generic class of decision problems, is adopted in this paper to achieve fast mode decision for the H.264/Scalable Video Coding standard. A constrained model is developed with optimal stopping, and the solutions to this model are employed to initialize the candidate mode list and predict the early termination. Comprehensive simulation results are conducted to demonstrate that the proposed method strikes a good balance between low encoding complexity and high coding efficiency.     

Reader Coverage Analysis for Multi-Carrier Passive UHF RFID Systems

Applications of passive radio frequency identification (RFID) systems have gained considerable attentions in recent years. Because a passive tag must obtain its operating power from a continuous wave transmitted from a reader in a conventional RFID system, reader coverage is limited. Thus, expanding reader coverage is a current goal in RFID research. In this work, passive tags are provided with additional operating power via continuous waves in multiple frequency bands. In an interrogation region, continuous wave emitters, which provide additional operating power to passive tags, are deployed according to the base station configuration in a cellular phone system. Because transmission power of continuous wave emitters must consider the reader command demodulation constraint and minimum operating power required by a tag, transmission power of continuous wave emitters must be chosen carefully. A method for analyzing reader coverage in multi-carrier passive UHF RFID systems is derived in this work. Assuming all tags are uniformly distributed in an interrogation region, the optimal continuous wave emitter transmission power that achieves the largest reader coverage can be analytically determined. Simulation results verify that continuous wave emitters with suitable transmission power expand reader coverage in a multi-carrier passive UHF RFID system. Additionally, adjusting reader power in the forward (reader-to-tag) link duration can loosen the reader command demodulation constraint and thereby further expand reader coverage.     

Multicast Parametric Synchronous Sampling of 320-Gb/s Return-to-Zero Signal

Technology for simultaneous demultiplexing of subrate tributaries is described and applied to 320-Gb/s return-to-zero input. The parametric architecture is scalable with respect to processed input rate and relies on cascaded all-optical multicasting and subrate sampling. Processing of 320-Gb/s input was achieved by creating eight channel copies, followed by a 20-THz-wide parametric gate. Multicasting was based on a self-seeded two-pump broadband fiber-optic parametric amplifier. The architecture was used to demonstrate error-free parallel demultiplexing of eight 320-Gb/s tributary channels at 40 Gb/s.     

Enhanced microstrip filter design with a uniform dielectric overlay for suppressing the second harmonic response

Parallel-coupled microstrip filters are designed to suppress spurious response at twice the passband frequency (2f/sub o/) with a uniform dielectric overlay. The overlay dielectric is used to equalize the modal phase velocities of each coupled stage. Based on the method, we have a large degree of freedom in choosing thickness and permittivity of the overlay dielectric. The image impedances of all the coupled stages in such a filter need adjusting to complete the filter synthesis. Two filters are fabricated and measured results show a good agreement with the simulation. A suppression of at least 40 dB to the spurious responses at 2f/sub o/ is achieved.     

A Realistic Timing Test Model and Its Applications in High-Speed Interconnect Devices

This paper extends the timing test model in [5] to be more realistic by including the effects of the test fixtures between a device under test and a tester. The paper enables analyzing the trade-offs that arise between the predicted yield and the required overall test environment timing accuracy (OTETA) which involves the tester overall timing accuracy (OTA) and the test fixtures' impacts. We specifically focus on the application of the extended model to predict the test yield of standard high-speed interconnects, such as PCI Express, Parallel/Serial RapidIO, and HyperTransport. The extended model reveals that achieving an actual yield of 80% with a test escape of 300 DPM (Defects Per Million) requires an equivalent OTETA that is about half the acceptable absolute limit of the tested parameter. Baosheng Wang received his B.S. degree from Beijing University of Aeronautics and Astronautics (BUAA), Beijing, P.R. China, in 1997 and M.S. degree from Precision Instrument & Mechanical Engineering from the Tsinghua University, Beijing, P. R. China in 2000. In 2005, he received his Ph.D. degree in Electrical Engineering from the University of British Columbia (UBC), Vancouver, BC, Canada. During his Master study, he was doing MEMS, Micro Sensors and Digital Signal processing. From 2000 to 2001, he worked in Beijing Gaohong Telecommunications Company as a hardware engineer in ATM technology. Currently, he is a Design-for-Test (DFT) engineer at ATI Technologies Inc., Markham, Ontario, Canada. He publishes widely at international conferences and journals. His primary research interests are time-driven or timing-oriented testing methodologies for System on-a-Chip (SoC). These fields include test time reduction for SRAMs, accelerated reliability test for non-volatile memories, yield analysis for SoC timing tests, SoC path delay timing characterization and embedded timing measurements. Andy Kuo is currently a Ph.D student of System on a Chip (SoC) Research Lab at the Department of Electrical and Computer Engineering, University of British Columbia. He received his M.A.Sc. and B.A.Sc in electrical and computer engineering from University of British Columbia and University of Toronto in 2004 and 2002 respectively. His research interests include high-speed signal integrity issues, jitter measurement, serial communications. Touraj Farahmand received the B.Sc. degree in Electrical Engineering from Esfahan University of Technology, Esfahan, Iran in 1989 and the M.Sc. in Control Engineering from Sharif university of Technology, Tehran, Iran in 1992. After graduation, he joined the Electrical and Computer Research center of Esfahan University of Technology where he was involved in the DSP algorithm development and design and implementation of the control and automation systems. Since October 2001, he has been working in the area of high-speed signal timing measurement at SoC (System-on-a-Chip) lab of UBC (University of British Columbia) as a research engineer. His research interests are signal processing, jitter measurement, serial communication and control. André Ivanov is Professor in the Department of Electrical and Computer Engineering, at the University of British Columbia. Prior to joining UBC in 1989, he received his B.Eng. (Hon.), M. Eng., and Ph.D. degrees in Electrical Engineering from McGill University. In 1995–96, he spent a sabbatical leave at PMC-Sierra, Vancouver, BC. He has held invited Professor positions at the University of Montpellier II, the University of Bordeaux I, and Edith Cowan University, in Perth, Australia. His primary research interests lie in the area of integrated circuit testing, design for testability and built-in self-test, for digital, analog and mixed-signal circuits, and systems on a chip (SoCs). He has published widely in these areas and holds several patents in IC design and test. Besides testing, Ivanov has interests in the design and design methodologies of large and complex integrated circuits and SoCs. Dr. Ivanov has served and continues to serve on numerous national and international steering, program, and/or organization committees in various capacities. Recently, he was the Program Chair of the 2002 VLSI Test Symposium (VTS'02) and the General Chair for VTS'03 and VTS'04. In 2001, Ivanov co-founded Vector 12, a semiconductor IP company. He has published over 100 papers in conference and journals and holds 4 US patents. Ivanov serves on the Editorial Board of the IEEE Design and Test Magazine, and Kluwer's Journal of Electronic Testing: Theory and Applications. Ivanov is currently the Chair of the IEEE Computer Society's Test Technology Technical Council (TTTC). He is a Golden Core Member of the IEEE Computer Society, a Senior Member of the IEEE, a Fellow of the British Columbia Advanced Systems Institute and a Professional Engineer of British Columbia. Yong Cho received the B.S. degree from Kyung Pook National Unviersity, Korea, in 1981 and the M.S. degree from in electrical and computer engineering from the University of South Carolina, Columbia, S.C., in 1988 and the Ph.D. degree in electrical engineering and applied physics from Case Western Reserve University, Cleveland, OH, in 1992. He is currently a Professor with the Department of Electronics Engineering, Konkuk University, Seoul, Korea. His recent research interests include SoC Design and Verification, H/W and S/W co-design, and embedded programming on SoC. Sassan Tabatabaei received his PHD in Electrical Engineering from the University of British Columbia, Vancouver, Canada in 2000. Since then, he has held several senior technical positions at Vector12 Corp, Guide Technology, and Virage Logic. His professional and research interests include mixed-signal design and test, and signal integrity and jitter test methodologies for high-speed circuits and multi-Gbps serial interfaces. He has published several papers and holds a US patent in the area of timing and jitter measurement. Currently, he holds the position of the director for embedded test at Virage Logic Corporation.