Thin-film reactions during diffusion soldering of Cu/Ti/Si and Au/Cu/Al<Subscript>2</Subscript>O<Subscript>3</Subscript> with Sn interlayers

The multilayer thin-film systems of Cu/Ti/Si and Au/Cu/Al₂O₃ were diffusion-soldered at temperatures between 250°C and 400°C by inserting a Sn thin-film interlayer. Experimental results showed that a double layer of intermetallic compounds (IMCs) η-(Cu_0.99Au_0.01)₆Sn₅/δ-(Au_0.87Cu_0.13)Sn was formed at the interface. Kinetics analyses revealed that the growth of intermetallics was diffusion-controlled. The activation energies as calculated from Arrhenius plots of the growth rate constants for (Cu_0.99Au_0.01)₆Sn₅ and (Au_0.87Cu_0.13)Sn are 16.9 kJ/mol and 53.7 kJ/mol, respectively. Finally, a satisfactory tensile strength of 132 kg/cm² could be attained under the bonding condition of 300°C for 20 min.     

A simple simultaneous geometric and intensity correction method for echo-planar imaging by EPI-based phase modulation

A technique, based on Echo planar imaging (EPI)-based phase modulation factor maps, is described for correction of EPI distortions resulting from field inhomogeneity. In this paper, a phase modulation factor was employed to remove the distortions. The phase modulation factor was obtained experimentally by collecting EPI images with a spin-echo (TE) spacing, deltaTE, equal to the inter-echo time interval, T(i). Then, the distortions resulting from the field inhomogeneity were removed by modulating the kappa-space data with the phase modulation factor. One of the advantages of this method is that it requires only a few extra scans to collect the information on field inhomogeneity. The proposed method does not require a phase unwrapping procedure for field inhomogeneity correction and, hence, is easier to implement, compared to other techniques. In addition, it corrects geometric distortion as well as intensity distortions simultaneously, which is robust to external noise or estimation error in severely distorted images. In this work, we also compared the proposed technique with others including, a) interpolation method with EPI-based displacement maps, and b) modulation method with phase modulation factor maps generated from spin-echo images. The results suggest the proposed technique is superior in correcting severely distorted images.     

A new scheme for bidirectional WDM-PON using upstream and downstream channels generated by optical carrier suppression and separation technique

We propose a new bidirectional dense wavelength-division-multiplexing (DWDM)-based passive optical network using optical carrier suppression and separation technique to generate both upstream and downstream wavelength channels from a single laser. Thirty-two DWDM channels have been generated, and symmetric 10-Gb/s data transmission of a wavelength pair has been demonstrated.     

PVT-aware leakage reduction for on-die caches with improved read stability

Effectiveness of previous SRAM leakage reduction techniques vary significantly as the leakage variation gets worse with process and temperature fluctuation. This paper proposes a simple circuit technique that adaptively trades off overhead energy for maximum leakage savings under severe leakage variations. The proposed run-time leakage reduction technique for on-die SRAM caches considers architectural access behavior to determine how often the SRAM blocks should enter a sleep mode. A self-decay circuit generates a periodic sleep pulse with an adaptive pulse period, which puts the SRAM array into a sleep mode more frequently at high leakage conditions (fast process, high temperature) and vice versa. An 0.18-/spl mu/m 1.8-V 16-kbyte SRAM testchip shows 94.2% reduction in SRAM cell leakage at a performance penalty less than 2%. Measurement results also indicate that our proposed memory cell improves SRAM static noise margin by 25%.     

Compact 2.5 Gb/s Burst‐Mode Receiver with Optimum APD Gain for XG‐PON1 and GPON Applications

This letter presents a compact 2.5 Gb/s burst‐mode receiver using the first reported monolithic amplifier IC developed with 0.25 …m SiGe BiCMOS technology. With optimum avalanche photodiode gain, the receiver module can obtain a fast response, high sensitivity and wide dynamic range, satisfying the overhead timing and various power specifications for a 2.5 Gb/s next‐generation passive optical network (PON), as well as a legacy 1.25 Gb/s PON in the upstream.     

Fabrication of organic semiconductor crystalline thin films and crystals from solution by confined crystallization

Highly crystalline thin films of organic semiconductors processed from solution for electronic devices are difficult to achieve due to a slow and preferential three-dimensional growth of the crystals. Here we describe the development of a processing technique to induce a preferential two-dimensional crystalline growth of organic semiconductors by means of minimizing one dimension and confining the solution in two dimensions into a thin layer. The versatility of the process is demonstrated by processing small molecules (TIPS-pentacene and C₆₀) and a polymer (P3HT), all from solvents with a relatively low boiling point, to obtain crystalline thin films. The thin films show an improved in-plane packing of the molecules compared to films processed under similar conditions by spin coating, which is beneficial for the use in organic field-effect transistors.     

A Universal VLSI Architecture for Reed–Solomon Error-and-Erasure Decoders

This paper presents a universal architecture for Reed-Solomon (RS) error-and-erasure decoder. In comparison with other reconfigurable RS decoders, our universal approach based on Montgomery multiplication algorithm can support not only arbitrary block length but various finite-field degree within different irreducible polynomials. Moreover, the decoder design also features the constant multipliers in the universal syndrome calculator and Chien search block, as well as an on-the-fly inversion table for calculating error or errata values. After implemented with 0.18-mum 1P6M technology, the proposed universal RS decoder correcting up to 16 errors can be measured to reach a maximum 1.28 Gb/s data rate at 160 MHz. The total gates count is around 46.4 K with 1.21 mm² silicon area, and the average core power consumption is 68.1 mW.