Visual insights into high-resolution earthquake Simulations.

This study focuses on the visualization of a series of large earthquake simulations collectively called TeraShake. The simulation series aims to assess the impact of San Andreas Fault earthquake scenarios in Southern California. We discuss the role of visualization in gaining scientific insight and aiding unexpected discoveries.     

Exploiting ILP, TLP, and DLP with the polymorphous trips architecture

The Tera-op reliable intelligently adaptive processing system (TRIPS) architecture seeks to deliver system-level configurability to applications and runtime systems. It does so by employing the concept of polymorphism, which permits the runtime system to configure the hardware execution resources to match the mode of execution and demands of the compiler and application.     

Characterization of Ceramic Composite-Membranes Prepared by ORMOSIL Coating Sol

Sol-gel methods offer many advantages over conventional slip-casting, including the ability to produce ceramic membranes. They are purer, more homogeneous, more reactive and contain a wider variety of compositions. We produced ormosil sol using sol-gel process under different molecular weight of polymer species [polyethylene glycol (PEG) ] in total system [Tetraethyl ortho silicate(TEOS)-polyethylene glycol (PEG)]. The properties of as-prepared ormosil sol such as,viscosity, gelation time were characterized. Also, the ceramic membrane was prepared by dip-coating with synthetic sol and its micro-structure was observed by scanning electron microscopy. The permeability and rejection efficiency of membrane for oil/water emulsion were evaluated as cross-flow apparatus. The ormosil sol coated Membrane is easily formed by steric effect of polymer and it improves flux efficiency because infiltration into porous support decreased. Its flux efficiency is elevated about 200(1/m2·h) compared with colloidal sol coated membrane at point of five minutes from starting test.     

CDT进军P-OLED市场

发光聚合物P-OLED开发领导厂商并将P-OLED广泛应用在电子显示器产品上的剑桥显示技术公司(CDT),是一家于1992年在英国成立,以发展、制造并销售P-OLED材料与IP给显示器产业的公司。P-OLED隶属于有机发光二极管的一部份,是一种质地薄、重量轻且具功率效益的组件,当电流流过时就会发光。相较于其它平面显示器技术,如液晶显示器,它们提供更为强化的视觉体验与卓越的效能特性。在技术方面,2005年计有9家获授权公司给付权利金,授权金额总计达到420万美元。这些授权的客户包括Epson在内,Epson最近才发表一项使用OLED做为高亮度的光源,…     

Data retention characteristics of sub-100 nm NAND flash memory cells

In contrast to the conventional theories, we have revealed that the most distinguished mechanism in the data retention phenomenon after Fowler-Nordheim (FN) stress in sub-100 nm NAND Flash memory cells is the annihilation of interface states. Interface state generation rate increases rapidly as the channel width of NAND flash cell decreases. Comparison of interface states and stress-induced leakage current (SILC) component during retention mode shows that the annihilation of interface states strongly affects data retention characteristics of the programmed cells.     

Presenting information on the small-screen interface: effects of table formatting

This study explored strengths and limitations of table formatting choices by engaging twenty-eight participants in information searches in online tables, presented on a small-screen interface (Palm IIIc). Table length across conditions was held constant at three screens long (24 rows total) but varied from one to three screens wide (approximately 35, 70, and 105 characters per line). Target information was positioned in either the upper left, lower left, upper right, or lower right quadrants. Data collected were time on task, error rate, and level of participants' confidence in their answers. Experimenters found that increased horizontal scrolling imposed the heaviest burden on information search. This study supports restricting table widths to one screen on handheld computers. If necessary, however, tables can go to two screens wide without critical detriment to usability. While ruled line formatting is slightly better than interface character in providing visual support for the burden of horizontal scrolling, neither formatting option adequately compensates for the added burden.     

Origin of the threshold voltage instability in SiO/sub 2//HfO/sub 2/ dual layer gate dielectrics

The magnitude of the V/sub T/ instability in conventional MOSFETs and MOS capacitors with SiO/sub 2//HfO/sub 2/ dual-layer gate dielectrics is shown to depend strongly on the details of the measurement sequence used. By applying time-resolved measurements (capacitance-time traces and charge-pumping measurements), it is demonstrated that this behavior is caused by the fast charging and discharging of preexisting defects near the SiO/sub 2//HfO/sub 2/ interface and in the bulk of the HfO/sub 2/ layer. Based on these results, a simple defect model is proposed that can explain the complex behavior of the V/sub T/ instability in terms of structural defects as follows. 1) A defect band in the HfO/sub 2/ layer is located in energy above the Si conduction band edge. 2) The defect band shifts rapidly in energy with respect to the Fermi level in the Si substrate as the gate bias is varied. 3) The rapid energy shifts allows for efficient charging and discharging of the defects near the SiO/sub 2//HfO/sub 2/ interface by tunneling.     

Effect of exponentially graded base doping on the performance ofGaAs/AlGaAs heterojunction bipolar transistors

The authors have fabricated n-p-n GaAs/AlGaAs heterojunction bipolar transistors (HBTs) with base doping graded exponentially from 5×10¹⁹ cm^-3 at the emitter edge to 5×10¹⁸ cm^-3 at the collector edge. The built-in field due to the exponentially graded doping profile significantly reduces base transit time, despite bandgap narrowing associated with high base doping. Compared to devices with the same base thickness and uniform base doping of 1×10¹⁹ cm^-3 , the cutoff frequency is increased from 22 to 31 GHz and maximum frequency of oscillation is increased from 40 to 58 GHz. Exponentially graded base doping also results ill consistently higher common-emitter current gain than uniform base doping, even though the Gummel number is twice as high and the base resistance is reduced by 40%     

89-GHz fT room-temperature silicon MOSFETs

The authors report the implementation of deep-submicrometer Si MOSFETs that at room temperature have a unity-current-gain cutoff frequency (f_T) of 89 GHz, for a drain-to-source bias of 1.5 V, a gate-to-source bias of 1 V, a gate oxide thickness of 40 Å, and a channel length of 0.15 μm. The fabrication procedure is mostly conventional, except for the e-beam defined gates. The speed performance is achieved through an intrinsic transit time of only 1.8 ps across the active device region     

Synthesis and characterization of poly(siloxane-urethane)s

A series of polyurethane block copolymers based on hydroxy-terminated polydimethylsiloxane and poly(propylene glycol) soft segments of molecular weights 1818 and 2000, respectively, were synthesized. The hard segments consisted of 4,4′-diphenylnethane diisocyanate and 1,4-butanediol as the chain extender. Samples with different molar ratios were prepared. We tried to synthesize polydimethylsiloxane-based polyurethanes (PDMS-PU) containing a hard block as major fraction and a soft block as minor fraction for preparing toughened rigid systems. After a study of the pure polydimethylsiloxane-based polyurethane and poly(propylene glycol)-based polyurethane (PPG-PU), (mixed polyol)-based block copolymers and blends of PDMS-PU and PPG-PU were synthesized, and characterized by means of differential scanning calorimetry, tensile testing and scanning electron microscopy. In (mixed polyol)-based copolymers and lower hard-segment content blends, macro-phase separation occurred, but blends with higher hard-segment contents showed significant reduction in amounts of phase separation.